Real-Time Integrated ORBGRAND-Based Transceiver (RIOT)

Project Description

With the rapid advancements in high-speed computing and digital signal processing for the Internet of Things (IoT), the volume of data transmitted and received across multiple devices has increased exponentially. However, received data is often susceptible to corruption due to noise, necessitating the use of efficient decoding techniques to mitigate its effects and ensure data integrity. The recently proposed Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND) algorithm offers optimal decoding performance while remaining well-suited for hardware implementation. This project aims to develop a fully integrated, real-time ORBGRAND-based transceiver to evaluate its decoding efficiency under various channel noise conditions.

 Mentors

Rabia Yazicigil Kirby, PI Akshaya Bali Zeynep Ece Kizilates Arslan Riaz

The student researcher will develop a simplified transceiver using Software-Defined Radios (SDRs) integrated with Field-Programmable Gate Arrays (FPGAs) connected to an ORBGRAND chip for decoding. The objective of this project is to transmit data packets from a host PC through the SDR, receive them back, and remove the effect of noise using ORBGRAND. Additionally, different code rates will be applied to achieve the desired decoding performance under different channel scenarios. The performance of the ORBGRAND chip will be evaluated under various channel conditions, including correlated channels with high reflections and echoes, as well as direct line-of-sight in open space. Key performance metrics will include bit error rate across a range of signal-to-noise ratios (SNRs), decoding latency, and power consumption of the decoder.
• Using FPGA for chip testing
• Functionality verification and measurements of a digital chip
• Programming simple SDRs
• Forward Error Correction algorithms in digital communication systems

Timeline

Week 1: Learning forward error correction and introduction to FPGAs and SDRs
Week 2-3: Getting hands on experience with programming of FPGAs and SDRs
Week 4-6: Programming FPGAs to send and receive data from chip in real-time
Week 7-9: Real-time data transmission and reception of packets and decoding using the decoder chip.
Week 10: Demonstration of the system and evaluation of its performance