Content includes use of HDL (Verilog) for design, synthesis and simulation, and principles of register transfer level (RTL). Programmable logic, such as field programmable gate array (FPGA) devices, has become a major component of digital design. In this class the students learn how to write HDL models that can be automatically synthesized into integrated circuits such as FPGA. Laboratory and homework exercises include writing HDL models of combinational and sequential circuits, synthesizing models, performing simulation, and fitting to an FPGA by using automatic place and route. The course has lab orientation and is based on a sequence of Verilog design examples.

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