Extending the Smart Pixel Paradigm: Integrated Image Acquisition and Imaging Processing Circuitry, Todd A. Hinck, 2004
This dissertation is a detailed description of a biologically inspired image process system based on the Boundary Contour System/ Feature Contour System (BCS/FCS). The functional architecture of biological vision is vastly different from more traditional vision systems. In traditional vision systems, the emphasis is on high-speed circuitry in order to provide the computational power necessary. In contrast to this, biological systems leverage the computational requirements of visual processing using slow, low precision elements with distributed processing. In this new circuit architecture, the circuitry uses non-traditional algorithms designed with analog circuitry to extend the traditional smart pixel paradigm, which draws on the strengths of biological vision. The general approach used for designing the circuits is based on a current-mode design methodology. This choice of design methodology maximizes the circuitry's operating ranges by using low impedance nodes and by keeping the overall device sizes reasonable. Subsequently, most of the circuitry in the system is operated in the subthreshold regime to take advantage of its log-linear current relationship. Four main core circuit blocks are introduced, including two novel ones, which form the foundation of the described circuit architecture. Using these building blocks, detailed designs of all nine stages of the BCS/FCS are described and simulated to illustrate their spatial processing features. In addition, two VLSI chips representing Stage 1 and Stage 2 were built and tested. From the Stage 1 chip, the output of the shunting neuron circuitry demonstrates local adaptive gain control over three orders of magnitude. From the Stage 2 chip, electronically oriented, elliptical spatial filter kernels show outputs comparable to those used in orientation filtering. These two chips based on the proposed BCS/FCS architecture demonstrate the plausibility of implementing the entire model in VLSI.