Intel produces compilers that produce highly optimized code for their CPUs. As with all compilers, programs compiled with optimization should have their output double-checked for accuracy. If the numeric output is incorrect or lacks the desired accuracy less-aggressive compile options should be tried. The following table summarizes some relevant commands on the SCC:<\/p>\n
| Command<\/th>\n | Description<\/th>\n<\/tr>\n | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| module avail intel<\/td>\n | List available versions of the Intel compiler.<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| module load intel\/2023.1<\/td>\n | Load a particular version.<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| icc<\/td>\n | C compiler.<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| icpc<\/td>\n | C++ compiler<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| ifort<\/td>\n | Fortran compiler.<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| icx<\/td>\n | New generation C compiler. (intel\/2023.1 and newer only)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| icpx<\/td>\n | New generation C++ compiler. (intel\/2023.1 and newer only)<\/td>\n<\/tr>\n | ||||||||||||||||||||||||
| ifx<\/td>\n | New generation Fortran compiler. (intel\/2023.1 and newer only)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n Intel compiler modules after 2023.1 will only support the new generation compilers (icx, icpx, ifx) as Intel is retiring the older ones (icc, icpc, ifort). <\/strong><\/p>\n All compilers have manuals available, for example:<\/p>\n <\/p>\n These flags will produce executables that contain specific SIMD instructions which may effect compatibility with compute nodes on the SCC.<\/p>\n There is an alternate form of this flag, -x<\/em>, which uses the options given below with -ax<\/em>. However, code compiled with -x<\/em> will not execute at all on AMD processors so it is not recommended.<\/td>\n<\/tr>\n For example: \u00a0\u00a0 icx -c -O3 -mavx -axCORE-AVX2,CORE-AVX512 mycode.cpp<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n Most open source programs that compile from source code use the -O2 or -O3 flags.\u00a0 This will result in fast code that can run on any compute node on the SCC.\u00a0 The -fast flag can be problematic (due to its inclusion of the -xHost flag) when run on the login nodes as they are Broadwell architecture CPUs which support AVX2 instructions.\u00a0 Codes compiled with -fast will only be able to execute on Broadwell architecture compute nodes on the SCC.<\/p>\n Most codes will be well-optimized with the -O2 or -O3 flags.\u00a0 Programs that involve intensive floating-point calculations inside of loops can additionally be compiled with the -xarch<\/em> flag.\u00a0 For maximum cross-compatibility across the SCC compute nodes and probable highest performance a combination of flags should be used:<\/p>\n If benchmarking and testing of the compiled code does not show any improvement with the -x and -ax flags then they can be removed to improve compilation times.<\/p>\n Note that selecting specific SIMD instructions with the -xarch<\/em> flag alone will restrict compatibility with compute nodes unless the job is submitted with this qsub flag:\u00a0 -l cpu_arch=compatible_arch<\/em>. The compatible_arch<\/em> value is an architecture name that matches the SIMD instructions.\u00a0 In this example a code is compiled with AVX instructions and a Haswell architecture CPU is requested with qsub:<\/p>\n If a code is relatively small in scope it can be compiled as part of a queue job.\u00a0 For example, a job that is submitted to run on a Buy-in node equipped with an Ivybridge architecture CPU could be compiled with tunings for that node.\u00a0 As a precaution the source is copied into $TMPDIR:<\/p>\n <\/div>\n<\/div>\n\n","protected":false},"excerpt":{"rendered":" Intel produces compilers that produce highly optimized code for their CPUs. As with all compilers, programs compiled with optimization should have their output double-checked for accuracy. If the numeric output is incorrect or lacks the desired accuracy less-aggressive compile options should be tried. The following table summarizes some relevant commands on the SCC: Command Description…<\/p>\n","protected":false},"author":1692,"featured_media":0,"parent":78157,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/pages\/107600"}],"collection":[{"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/users\/1692"}],"replies":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/comments?post=107600"}],"version-history":[{"count":16,"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/pages\/107600\/revisions"}],"predecessor-version":[{"id":146593,"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/pages\/107600\/revisions\/146593"}],"up":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/pages\/78157"}],"wp:attachment":[{"href":"https:\/\/www.bu.edu\/tech\/wp-json\/wp\/v2\/media?parent=107600"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}} |