ECE Seminar with Vasileios Pavlidis

Truths and Lies about 3-D ICs Dr. Vasilis Pavlidis University of Manchester, United Kingdom Faculty Host: Ayse Coskun Refreshments will be served outside Room 339 at 10:45 a.m. Abstract: Three-dimensional integration has been a hot research topic for the last few years, primarily due to its potential to constitute a track for continuing microelectronics evolution. In addition, there have been a lot of discussions as to whether this technology can alleviate the pressing issues in circuit and, more broadly, in integrated system design. This talk intends to shed light to several issues, that if not carefully considered in the design process, can reduce the promised benefits. The talk will emphasize the different aspects of manufacturing and environmental variations for 3-D ICs as compared to planar 2-D ICs. New models to describe and practices to confine variability in 3-D ICs will be presented. These techniques are related to the synchronization and thermal management tasks on the system and overlooking specific features of a 3-D system can lead to substantially lower benefits and expensive design decisions. Furthermore, considering the importance of cost issues of 3D technology, a technique to exploit process variability to improve the overall revenues that can result from a multi-tier stack will also be described. About the Speaker: Vasilis Pavlidis received his MSc and PhD degrees from the University of Rochester, Rochester, N.Y., in 2003 and 2008, respectively, all in Electrical Engineering. From 2008 to 2012, he has been a post-doc with the Integrated Systems Laboratory at EPFL, Switzerland. In September 2012, he was appointed to Lecturer at the Computer Science department of the University of Manchester within the Advanced Processor Technologies group. His research interests are in the area of interconnect modeling and analysis, 3-D integration, and general VLSI design.