ECE Prospectus Defense: Zihao Yuan
- Starts: 1:00 pm on Friday, October 30, 2020
- Ends: 3:00 pm on Friday, October 30, 2020
Title: Modeling Emerging On-Chip Cooling Technologies and Optimization via Machine Learning
Advisor: Professor Ayse Coskun
Chair: Prof. Ajay Joshi, ECE
Committee: Prof. Rabia Yazicigil, ECE; Prof. Sherief Reda from Brown University
Abstract: Over the last few decades, processor performance has continued to grow due to the down-scaling of the transistor dimensions. This performance boost has translated into high power densities and localized hot spots, which not only decrease the lifetime of processors but also increase transistor delays as well as leakage power. Conventional on-chip cooling solutions are often not sufficient to efficiently mitigate such high-power-density hot spots. Emerging cooling technologies such as liquid cooling via microchannels, thermoelectric coolers (TECs), two-phase vapor chambers (VCs), and hybrid cooling options (e.g., of liquid cooling via microchannels and TECs) have the potential to provide better cooling performance compared to conventional cooling solutions. However, these potential solutions’ cooling performance and cooling power vary significantly based on their design and operational parameters (such as liquid flow velocity, evaporator design, TEC current, etc.) and the chip specifications. Given the vast solution space of possible cooling solutions (including possible hybrids) and cooling subsystem parameters, the optimal solution search time is prohibitively time-consuming. To minimize the cooling power overhead while satisfying chip thermal constraints, there is a need for an optimization flow that enables rapid and accurate selection of the best cooling solution and the associated cooling parameters for a given chip design and workload profile.
This thesis claims that combining a compact thermal modeling methodology with deep learning (DL) models have the potential to rapidly and accurately predict the optimal cooling solution and its cooling parameters for arbitrary chip designs. The thesis aims to realize this optimization flow through two fronts. First, it proposes a parallel compact thermal simulator, PACT, that enables speedy and accurate standard-cell level to architectural level thermal analysis for processors. PACT has high extensibility and applicability, and can be used to model and evaluate the thermal behaviors of emerging integration (e.g., monolithic 3D) and cooling technologies (e.g., two-phase vapor chambers). In addition, PACT can be used to generate the necessary training data for DL models and evaluate the thermal profile for a given processor design. Second, this thesis proposes a systematic way to create novel DL models to predict the optimal cooling methods and cooling parameters for a given chip design at design time as well as automatically tune the cooling parameters at runtime. Through experiments based on various real-world high-power-density chips and their floorplans, this thesis aims to demonstrate that using DL models substantially minimizes the search time while achieving the same search accuracy compared to brute force methods.