{"id":42,"date":"2011-11-03T22:26:52","date_gmt":"2011-11-04T02:26:52","guid":{"rendered":"https:\/\/www.bu.edu\/icas\/?page_id=42"},"modified":"2026-05-20T15:54:56","modified_gmt":"2026-05-20T19:54:56","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.bu.edu\/icas\/publications\/","title":{"rendered":""},"content":{"rendered":"<h3>2026<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[EURO-PAR 2026]<\/strong>\u00a0S. Guzelhan, F. Acun, C. Hankendi, A. Coskun, and A. Joshi, &#8220;Privacy-Preserving Data Center Demand Response Participation using Multi-Party Computation,&#8221; to appear in International European Conference on Parallel and Distributed Computing (Euro-Par) 2026.<\/li>\n<li style=\"text-align: justify;\"><strong>[JETC 2026]<\/strong> F. Fayza, C. Demirkiran, G. Yang, H. Chen, C-K. Liu, A. Mohan, H. Errahmouni, S. Yun, M. Imani, D. Zhang, D. Bunandar, and A. Joshi, &#8220;PhotoHDC: An Electro-Photonic Accelerator for Hyperdimensional Computing,&#8221; to appear in ACM Journal on Emerging Technologies in Computing Systems (JETC) 2026.<\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2026]<\/strong> S. Karimi, G. Yang, C. Ocampo, A. Joshi, and A. Coskun, &#8220;<span>SCARLET: A Scalable OPCM-Based Accelerator for Transformer Inference with Tiled Crossbars<\/span>,&#8221; to appear in Proc. Design, Automation and Test in Europe (DATE) 2026.<\/li>\n<\/ul>\n<h3>2025<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[NATURE COMM PHY 2025]<\/strong> F. Fayza, C. Demirkiran, S. P. Rao, D. Bunandar, U. Gupta, and A. Joshi, &#8220;Photonics for Sustainable AI,&#8221; to appear in Nature Communications Physics 2025.<\/li>\n<li style=\"text-align: justify;\"><strong>[ICCAD 2025]<\/strong> F. Fayza, C. Demirkiran, S. Rao, D. Bunandar, U. Gupta, and A. Joshi, &#8220;EPiCarbon: A Carbon Modeling Tool for Electro-Photonic Accelerators,&#8221; in Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) 2025. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2025\/Fayza_ICCAD_2025.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ICCAD 2025]<\/strong> R. Bao, F. Cai, S. Chen, A. Joshi, D. Bunandar, and R. Kumar, &#8220;Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization,&#8221; in Proc. IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) 2025. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2025\/Bao_ICCAD_2025.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ISCA 2025]<\/strong> Y. Li, Y. Bao, G. Wang, X. Mei, P. Vaid, A. Ghosh, A. Jog, D. Bunandar, A. Joshi, and Y. Sun, &#8220;TrioSim: A Lightweight Simulator for Large-Scale DNN Workloads on Multi-GPU Systems,&#8221; in Proc. International Symposium on Computer Architecture (ISCA) 2025. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2025\/TrioSim_ISCA_2025.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[HPCA 2025]<\/strong> H. Song, G. Jonatan, W. Xiangyu, H. Cho, K. Shivdikar, J. Abellan, A. Joshi, D. Kaeli, and J. Kim, &#8220;<span>PIMnet: A Domain-Specific Network for Efficient Collective <\/span><span>Communication in Scalable PIM,&#8221; in Proc. IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2025.\u00a0<\/span><span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2025\/PIMnet_HPCA_2025.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[IEEE CAS 2025]<\/strong> K. Lee, M. Ashok, S. Maji, R. Agrawal, A. Joshi, M. Yan, J. S. Emer, and A. P. Chandrakasan, &#8220;Secure Machine Learning Hardware: Challenges and Progress,&#8221; in IEEE Circuits and Systems Magazine, vol. 25, no. 1, pp. 8-34, 2025. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2025\/Lee_CAS.pdf\">(pdf)<\/a><\/span><\/li>\n<\/ul>\n<h3>2024<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[MICRO 2024]<\/strong> G. Yang, S. Karimi, C. Ocampo, A. Coskun, and A. Joshi, &#8220;SOPHIE: A Scalable Recurrent Ising Machine Using Optically Addressed Phase Change Memory,&#8221; in Proc. IEEE\/ACM International Symposium on Microarchitecture (MICRO) 2024. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/opcm_ising_micro_2024.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[NATURE COMM 2024]<\/strong> C. Demirkiran, L. Nair, D. Bunandar, and A. Joshi, &#8220;A Blueprint for Precise and Fault-tolerant Analog Neural Networks,&#8221; in Nature Communications 2024. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/demirkiran-nature-2024.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISCA 2024]<\/strong> C. Demirkiran, G. Yang, D. Bunandar, and A. Joshi, &#8220;Mirage: An RNS-Based Photonic Accelerator for DNN Training,&#8221; Proc. International Symposium on Computer Architecture (ISCA) 2024. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/rns_training_isca2024.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ISCA 2024]<\/strong> R. Agrawal, A. Chandrakasan, and A. Joshi, &#8220;HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping,&#8221; in Proc. International Symposium on Computer Architecture (ISCA) 2024. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/fhe_parallelized_bootstrapping_isca_2024.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ISCA 2024]<\/strong> K. Shivdikar, N. Agostini, M. Jayaweera, G. Jonatan, J. Abellan, A. Joshi, J. Kim, and D. Kaeli, &#8220;NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator,&#8221; in Proc. International Symposium on Computer Architecture (ISCA) 2024. <span><a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/neurachip_isca_2024.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[SIGMETRICS 2024]<\/strong> <span>G. Jonatan, H. Cho, H. Son, X. Wu, N. Livesay, E. Mora, K. Shivdikar, J. L. Abell\u00e1n, A. Joshi, D. Kaeli, and J. Kim, &#8220;Scalability Limitations of Processing-in-Memory using Real System Evaluations,&#8221; ACM Sigmetric \/ IFIP Performance, Proc. ACM on Measurement and Analysis of Computing Systems (POMACS) 2024. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/pim_sigmetrics_2024.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2024]<\/strong> C. Rajapaksha, L. Delshadtehrani, R. Muri, M. Egele and A. Joshi, &#8220;IOMMU Deferred Invalidation Vulnerability: Exploit and Defense,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2024. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2024\/iommu_date_2024.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2023<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[MICRO 2023]<\/strong> R. Agrawal, L. Castro, C. Juvekar, A. Chandrakasan, V. Vaikuntanathan, and A. Joshi, &#8220;MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption&#8221; in Proc. IEEE\/ACM International Symposium on Microarchitecture (MICRO) 2023.\u00a0<a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/Agrawal_MICRO_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[MICRO 2023]<\/strong> K. Shivdikar, Y. Bao, R. Agrawal, M. Shen, G. Jonatan, E. Mora, A. Ingare, N. Livesay, J. Abellan, J. Kim, A. Joshi, and D. Kaeli, &#8220;GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption&#8221; in Proc. IEEE\/ACM International Symposium on Microarchitecture (MICRO) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/Shivdikar_Micro_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2023]<\/strong> Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, &#8220;RISE: RISC-V SoC for En\/decryption Acceleration on the Edge for Homomorphic Encryption,&#8221; in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/Azad_TVLSI_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[JETC 2023] <\/strong>C. Demirkiran, F. Eris, G. Wang, J. Elmhurst, N. Moore, N. Harris, N. Basumallik, V. Reddi, A. Joshi and D. Bunandar, &#8220;An Electro-Photonic System for Accelerating Deep Neural Networks,&#8221; in ACM Journal on Emerging Technologies in Computing Systems (JETC) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/Demirkiran_JETC_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISLPED 2023]<\/strong> G. Yang, C. Demirkiran, Z. Kizilates, C. Ocampo, A. Coskun, and A. Joshi, &#8220;Processing-in-Memory using Optically-Addressed Phase Change Memory,&#8221; in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/opcm_pim_islped_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SNAP-MLSys 2023]<\/strong> C. Demirkiran, R. Agrawal, V. Reddi, D. Bunandar and A. Joshi, &#8220;Leveraging Residue Number System for Designing High-Precision Analog Deep Neural Network Accelerators,&#8221; in Workshop on Systems for Next-Gen AI Paradigms (SNAP), co-located with Conference on Machine Learning and Systems (MLSys) 2023. <a href=\"https:\/\/arxiv.org\/pdf\/2306.09481.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SLCA 2023]<\/strong> R. Agrawal and A. Joshi, &#8220;Architecting Computing Systems for Fully Homomorphic Encryption,&#8221; Synthesis Lectures on Computer Architecture (SLCA) 2023. <a href=\"https:\/\/link.springer.com\/book\/9783031317538\">(link)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[IEEE MICRO 2023]<\/strong> N. Livesay, G. Jonatan, E. Mora, K. Shivdikar, R. Agrawal, A Joshi, J. L. Abell \u0301an, J. Kim, D. Kaeli, &#8220;Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs,&#8221; in Proc. IEEE Micro 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/livesay_micro_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HOST 2023]<\/strong> S. Canakci, C. Rajapaksha, A. Nataraja, L. Delshadtehrani, M. Taylor, M. Egele and A. Joshi, &#8220;ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance,&#8221; in Proc. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/profuzz_host_2023.pdf\">(pdf)<\/a><strong> (BEST PAPER AWARD)<\/strong><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2023]<\/strong> C. Rajapaksha, L. Delshadtehrani, M. Egele and A. Joshi, &#8220;SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/sigfuzz_date_2023.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HPCA 2023]<\/strong> R. Agrawal, L. DeCastro, G. Yang, C. Juvekar, R. Yazicigil, A. Chandrakasan, V. Vaikuntanathan and A. Joshi, &#8220;FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption,&#8221; in Proc. IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2023. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2023\/fhe_accelerator_fpga_hpca2023.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3><strong>2022<\/strong><\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[TACO 2022]<\/strong> F. Eris, M. Louis, K. Eris, J. Abellan and A. Joshi, &#8220;Puppeteer: A Random Forest-based Manager for Hardware Prefetchers across the Memory Hierarchy,&#8221; in ACM Transactions on Architecture and Code Optimization (TACO) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/puppeteer_taco_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TACO 2022]<\/strong> A. Narayan, Y. Thonnart, P. Vivet, A. Coskun and A. Joshi, &#8220;Architecting Optically-Controlled Phase Change Memory,&#8221; in ACM Transactions on Architecture and Code Optimization (TACO) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/opcm_taco_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[PACT 2022]<\/strong> Y. Bao, Y. Sun, Z. Feric, M. Shen, M. Weston, J. L. Abell\u00e1n, T. Baruah, J. Kim, A. Joshi and D. Kaeli, &#8220;NaviSim: A Highly Accurate GPU Simulator for AMD RDNA GPUs,&#8221; in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/navisim_pact_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SEED 2022]<\/strong> K. Shivdikar, G. Jonatan, E. Mora, N. Livesay, R. Agrawal, A. Joshi, J. L. Abell\u00e1n, J. Kim and D. Kaeli, &#8220;Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs,&#8221; in Proc. IEEE International Symposium on Secure and Private Execution Environment Design (SEED) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/fhe_gpu_seed_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HOTCHIPS 2022]<\/strong> N. Harris, D. Bunandar, A. Joshi, A. Basumallik and R. Turner, &#8220;Passage: A Wafer-Scale Programmable Photonic Communication Substrate,&#8221; in Proc. IEEE Hot Chips Symposium (HCS) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/passage_hotchips_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISLPED 2022]<\/strong> Z. Azad, G. Yang, R. Agrawal, D. Petrisko, M. Taylor and A. Joshi, &#8220;RACE: RISC-V SoC for En\/decryption ACceleration on the Edge for Homomorphic Computation,&#8221; in Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/race_islped_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISMRM 2022]<\/strong> M. Louis, H. Liao, R. Singh, J. Lee, A. Joshi and A. Lin. &#8220;Using Machine Learning to Identify Metabolite Spectral Patterns that Reflect Outcome after Cardiac Arrest,&#8221; in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting &amp; Exhibition 2022.<\/li>\n<li style=\"text-align: justify;\"><strong>[ISMRM 2022] <\/strong>M. Louis, H. Liao, A. Joshi and A. Lin. &#8220;The Effect of Differences in MRS Parameters on Data Harmonization of Normative Data,&#8221; in International Society for Magnetic Resonance in Medicine (ISMRM) Annual Meeting &amp; Exhibition 2022.<\/li>\n<li style=\"text-align: justify;\"><strong>[ASIACCS 2022]<\/strong> S. Canakci, N. Matyunin, K. Graffi, A. Joshi and M. Egele, &#8220;TargetFuzz: Using DARTs to Guide Directed Greybox Fuzzers,&#8221; in Proc. ACM ASIA Conference on Computer and Communications Security (ASIACCS) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/targetfuzz-asiaccs-2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2022]<\/strong> P. Das, A. Joshi and H. Kapoor, &#8220;Hydra: A Near Hybrid Memory Accelerator for CNN Inference,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2022. <a href=\"https:\/\/bu-icsg.github.io\/publications\/2022\/hydra_date_2022.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SPRINGER 2022] <\/strong>Y. Ma, B. Joardar, P. Pande and A. Joshi, \u201cInterconnect and Integration Technology\u201d to appear in Emerging Computing: From Devices to Systems &#8211; Looking Beyond Moore and Von Neumann, Springer Nature 2022.<\/li>\n<\/ul>\n<h3>2021<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ACSAC 2021]<\/strong> L. Delshadtehrani, S. Canakci, W. Blair, M. Egele and A. Joshi, &#8220;FlexFilt: Towards Flexible Instruction Filtering for Security,&#8221; in Proc. Annual Computer Security Applications Conference (ACSAC) 2021. <span><a href=\"http:\/\/people.bu.edu\/joshi\/files\/Delshadtehrani_Acsac_2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[MICRO 2021]<\/strong> J. Ahn, J. Kim, H. Kasan, L. Delshadtehrani, W. Song, A. Joshi and J. Kim, &#8220;Network-on-Chip Microarchitecture-based Covert Channel in GPUs,&#8221; in Proc. IEEE\/ACM International Symposium on Microarchitecture (MICRO) 2021. <span><a href=\"http:\/\/people.bu.edu\/joshi\/files\/Ahn_Micro_2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[DAC 2021]<\/strong> S. Canakci, L. Delshadtehrani, F. Eris, M. Taylor, M. Egele and A. Joshi, &#8220;<span>DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing<\/span>,&#8221; in Proc. Design Automation Conference (DAC) 2021.<span> <a href=\"http:\/\/people.bu.edu\/joshi\/files\/Hardware_Fuzzing_DAC_2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[MLArchSys-ISCA 2021]<\/strong> F. Eris, M. Louis, S. Canakci, J. Abellan and A. Joshi, &#8220;Custom Tailored Suite of Random Forests for Prefetcher Adaptation,&#8221; ML for Computer Architecture and Systems Workshop, co-located with International Symposium on Computer Architecture (ISCA) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/puppeteer_mlarchsys_2021.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISMRM 2021]<\/strong> M. Louis, E. Coello, H. Liao, A. Joshi and A. Lin, &#8220;Quantification of Unsuppressed Water Spectrum using Autoencoder with Feature Fusion,&#8221; in <span>International Society for Magnetic Resonance in Medicine (ISMRM)\u00a0Annual Meeting &amp; Exhibition 2021.<\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[IEEE D&amp;T 2021]<\/strong> B. Zhou. R. Jahanshahi, M. Egele and A. Joshi, &#8220;<span>A Cautionary Tale about Detecting Malware Using Hardware Performance Counters and Machine Learning<\/span>,&#8221; in <span>Special Issue of <\/span><span>IEEE Design &amp; Test <\/span><span>on Hardware Security Top Picks, vol. 38, no. 3, pp. 39-50, June 2021<\/span>. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhou_2021_DT.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISPASS 2021]<\/strong> Z. Azad, R. Sen, K. Park and A. Joshi, &#8220;<span>Hardware Acceleration for DBMS Machine Learning Scoring:\u00a0<\/span><span>Is It Worth the Overheads?<\/span>&#8221;\u00a0<span>in Proc. IEEE International Symposium on Performance Analysis of Systems\u00a0and Software (ISPASS) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/database_acceleration_fpga_ispass_2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ISPASS 2021]<\/strong> M. Buch, Z. Azad, A. Joshi and V. Reddi, &#8220;<span>AI Tax in Mobile SoCs: Quantifying the End-to-End AI\u00a0<\/span><span>Application Performance on Smartphones,<\/span>&#8221; <span>in Proc. IEEE International Symposium on Performance Analysis of Systems\u00a0and Software (ISPASS) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/mobile_soc_ispass_2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[ISPASS 2021]<\/strong> <span>T. Baruah,\u00a0<\/span><span>K. Shivdikar,\u00a0<\/span><span>S. Dong, Y.Sun, S. Mojumder, K. Jung, J.<\/span><span>\u00a0Abell\u00e1n, Y. Ukidave, A. Joshi, J. Kim and D. Kaeli, &#8220;GNNMark: A Benchmark Suite to Characterize Graph Neural\u00a0Network Training on GPUs,&#8221; in Proc. IEEE International Symposium on Performance Analysis of Systems\u00a0and Software (ISPASS) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/gnnmark-ispass-2021.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2021]<\/strong> Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan and A. Joshi, &#8220;TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/Ma_TAP-2.5D-DATE2021.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2021]<\/strong> L. Delshadtehrani, S. Canakci, M. Egele and A. Joshi, &#8220;SealPK: Sealable Protection Keys for RISC-V,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2021. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/SealPK_DATE_2021.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[CRC 2021]<\/strong> A. Narayan, A. Joshi and A. Coskun, &#8220;System-Level Management of Silicon-Photonic Networks in 2.5D Systems,&#8221; in <span>Silicon Photonics for High Performance Computing and Beyond<\/span>, CRC 2021.<\/li>\n<li style=\"text-align: justify;\"><strong>[TCAD 2021]<\/strong> B. Zhou, A. Aksoylar, K. Vigil, R. Adato, J. Tan, B. Goldberg, M. Selim Unlu, and A. Joshi, &#8220;Hardware Trojan Detection using Backside Optical Imaging,&#8221; in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, <span>vol. 40, no. 1, pp. 24-37, Jan. 2021<\/span>. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhou_TCAD_2021.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2020<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[PACT 2020]<\/strong> T. Baruah, Y. Sun, S. Mojumder, J. Abellan, Y. Ukidave, A. Joshi, N. Rubin, J. Kim and D. Kaeli, &#8220;Valkyrie: Leveraging Inter-TLB Locality to Enhance GPU Performance,&#8221; in Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT) 2020. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/pactfp17-baruahA.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HPEC 2020]<\/strong> A. Narayan, A. Joshi and A. Coskun, &#8220;Bandwidth Allocation in Silicon Photonic Networks using Application Instrumentation,&#8221; in Proc. IEEE High Performance Extreme Computing Conference (HPEC) 2020. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/Narayan_HPEC20.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[USENIX-SECURITY 2020] <\/strong>L. Delshadtehrani, S. Canakci, B. Zhou, S. Eldridge, A. Joshi and M. Egele, &#8220;PHMon: A Programmable Hardware Monitor and its Security Applications,&#8221; in Proc. USENIX Security Symposium 2020.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/sec20-delshadtehrani.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ACCESS 2020]<\/strong> N. Zaraee, B. Zhou, K. Vigil, M. Shahjamali, A. Joshi and M. Selim Unlu, &#8220;Gate-level Validation of Integrated Circuits with Structured-Illumination Read-out of Embedded Optical Signatures,&#8221; in Proc. IEEE Access, vol. 8, pp. 70900-70912, 2020. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/zaraee-access-2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[IEEE MICRO 2020]<\/strong> D. Petrisko, F. Gilani, M. Wyse, T. Jung, S. Davidson, P. Gao, C. Zhao, Z. Azad, S. Canakci, B. Veluri, T. Guarino, A. Joshi, M. Oskin, and M. Taylor, &#8220;BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs,&#8221; IEEE Micro, vol. 40, no. 4, pp. 93-102, 2020. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/PetriskoMicro2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DIMVA 2020]<\/strong> S. Canakci, L. Delshadtehrani, B. Zhou, A. Joshi and M. Egele, &#8220;Efficient Context-Sensitive CFI Enforcement through a Hardware Monitor,&#8221; in Proc. Conference on Detection of Intrusions and Malware &amp; Vulnerability Assessment (DIMVA) 2020.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/cfi-dimva-2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TCAD 2020]<\/strong> A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma*, A. Narayan and V. Srinivas, &#8220;Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5D Systems,&#8221; in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, <span>vol. 39, no. 12, pp. 5183-5196, Dec. 2020<\/span>. (<strong>*Lead Author<\/strong>).\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Ma_TCAD_2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISMRM 2020]<\/strong> M. Louis, E. Coello, H. Liao, A. Joshi, and A. Lin, &#8220;Quantification of Non-Water-Suppressed Proton Spectroscopy using Deep Neural Networks,&#8221; in Proc. International Society for Magnetic Resonance in Medicine (ISMRM) <span>Annual Meeting &amp; Exhibition<\/span>\u00a02020.<\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2020]<\/strong>\u00a0A. Narayan, Y. Thonnart, P. Vivet, A. Joshi and A. Coskun, &#8220;System-level Evaluation of Chip-Scale Silicon-Photonic Networks for Emerging Data-Intensive Applications,&#8221; in\u00a0Proc. Design, Automation and Test in Europe (DATE) 2020.\u00a0<strong>(Invited paper)<\/strong>\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/sipho_invited_date_2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HPCA 2020]<\/strong> T. Baruah, Y. Sun, A. Dincer, S. Mojumder, J. Abellan, Y. Ukidave, A. Joshi, N. Rubin, J. Kim and D. Kaeli, &#8220;Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU systems,&#8221; in Proc. International Symposium on High-Performance Computer Architecture (HPCA) 2020.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/demand_paging_hpca2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2020]<\/strong>\u00a0Z. Azad, M. S. Louis, L. Delshadtehrani, A. Ducimo, S. Gupta, P. Warden, V. J. Reddi and A. Joshi, \u201cAn End-to-end RISC-V Solution for ML on the Edge Using In-pipeline Support,\u201d in Proc. Boston area ARChitecture (BARC) Workshop 2020. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/rvmlpu-barc-2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2020]\u00a0<\/strong>L. Delshadtehrani, S. Canakci, B. Zhou, S. Eldridge, A. Joshi and M. Egele, \u201cA Programmable Hardware Monitor for Security of RISC-V Processors\u201d in Proc. Boston area ARChitecture (BARC) Workshop 2020.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/PHMon-barc-2020.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2020]<\/strong>\u00a0Z. Azad, S. Canakci, S. Davidson, P. Gao, F. Gilani, T. Guarino, T. Jung, D. Petrisko, B. Veluri, M. Wyse, C. Zhao, M. Oskin, M. Bedford Taylor and A. Joshi, \u201cBlackParrot: An Open-Source RISC-V Multicore Processor A core for and by the world!\u201d in Proc. Boston area ARChitecture (BARC) Workshop 2020.<\/li>\n<\/ul>\n<h3>2019<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ISCA 2019] <\/strong>Y. Sun,\u00a0T. Baruah, S. Mojumder,\u00a0S. Dong, X. Gong, S. Treadway,\u00a0Y. Bao,\u00a0S. Hance,\u00a0C McCardwell, V. Zhao,\u00a0H. Barclay,\u00a0A. Ziabari,\u00a0Z. Chen,\u00a0R. Ubal,\u00a0J. Abell\u00e1n,\u00a0J. Kim,\u00a0A. Joshi and D. Kaeli,\u00a0&#8220;MGPUSim: Enabling Multi-GPU Performance Modeling and Optimization,&#8221; in Proc. International Symposium on Computer Architecture (ISCA) 2019. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/mgpusim-isca2019.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[CARRV-ISCA 2019]<\/strong> M. Louis, Z. Azad, L. Delshadtehrani, P. Warden, V. Reddi, S. Gupta and A. Joshi, &#8220;Towards Deep Learning using TensorFlow Lite on RISC-V,&#8221; in Proc.\u00a0Workshop on Computer Architecture Research with RISC-V (CARRV) held in conjunction with International Symposium on Computer Architecture (ISCA) 2019. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/tflowlite-carrv-2019.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[GOMACTECH 2019]<\/strong> Z. Azad, L. Delshadtehrani, F. Gilani, T. Jung, K. Lim, D. Petrisko, M. Wyse, B. Zhou, T. Guarino, B. Veluri, Y. Wang, M. Oskin, A. Joshi, M. Taylor, \u201cThe BlackParrot Processor: An Open-Source Industrial-Strength RV64G Multicore Processor,\u201d in Proc. Government Microcircuit Application\u2019s Critical Technology Conference (GOMACTech) 2019.<\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2019]<\/strong> B. Zhou, A. Gupta, R. Jahanshahi, M. Egele and A. Joshi<span>,\u00a0<\/span>&#8220;Can We Reliably Detect Malware Using Hardware Performance Counters?,&#8221; in\u00a0<span>Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2019<\/span>.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/zhou-barc-2019.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2019]<\/strong> S. Mojumder, M. Louis, Y. Sun, A. Ziabari, J. Abellan, J. Kim, D. Kaeli and A. Joshi<span>,\u00a0<\/span>&#8220;Evaluation of Volta-based DGX-1 System Using DNN Workloads,&#8221; in\u00a0<span>Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2019<\/span>.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/mojumder-barc-2019.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2018<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ICCAD 2018]<\/strong> A. Coskun, F. Eris*, A. Joshi, A. Kahng, Y. Ma and V. Srinivas, &#8220;A Cross-Layer Methodology for Design and Optimization of Networks in 2.5D Systems,&#8221; in Proc. International Conference on Computer-Aided Design (ICCAD) 2018. (<strong>*Lead Author<\/strong>). <a href=\"http:\/\/people.bu.edu\/joshi\/files\/interposer-nw-iccad-2018.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[IISWC 2018]<\/strong>\u00a0S. Mojumder, M. Louis, Y. Sun, A. Ziabari, J. Abellan, J. Kim, D. Kaeli and A. Joshi, &#8220;Profiling DNN Workloads on a Volta-based DGX-1 System,&#8221; in Proc. IEEE International Symposium on Workload Characterization (IISWC) 2018.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/evaluation-multi-gpu-iiswc-2018.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISMRM 2018]<\/strong>\u00a0M. Louis, M. Alosco, B. Rowland, H. Liao, J. Wang, R. Stern, A. Joshi, and A. Lin, &#8220;Biomarkers for CTE diagnosis in retired NFL players using Machine learning&#8221; in Proc. International Society for Magnetic Resonance in Medicine (ISMRM) <span>Annual Meeting &amp; Exhibition\u00a0<\/span>2018.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/cte-ismrm-2018.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ASIACCS 2018]<\/strong> B. Zhou, A. Gupta, R. Jahanshahi, M. Egele and A. Joshi, &#8220;Hardware Performance Counters Can Detect Malware: Myth or Fact?,&#8221; in Proc. ACM Asia Conference on Computer and Communications Security (ASIACCS) 2018.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/asia065-zhouA.pdf\">(pdf)<\/a>\u00a0<strong>(BEST PAPER AWARD)<\/strong><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2018]<\/strong> F. Eris, A. Joshi, A. Kahng, Y. Ma*, S. Mojumder and T. Zhang, &#8220;Leveraging Thermally-Aware Chiplet Organization in 2.5D Systems to Reclaim Dark Silicon,&#8221; in Proc. Design, Automation and Test in Europe (DATE) 2018. (<strong>*Lead Author<\/strong>).\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/dark-silicon-date-2018.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2018]<\/strong> A. Coskun,\u00a0<span>F. Eris, A. Joshi, A. Kahng, Y. Ma*, S. Mojumder and T. Zhang,\u00a0<\/span>&#8220;Reclaiming Dark Silicon Using Thermally-Aware Chiplet Organization in 2.5D Integrated Systems,&#8221; in\u00a0<span>Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2018.\u00a0<\/span>(<strong>*Lead Author<\/strong>).<\/li>\n<li style=\"text-align: justify;\"><strong>[CAL 2018]<\/strong> L. Delshadtehrani, S. Eldridge, S. Canakci, M. Egele and A. Joshi, &#8220;Nile: A Programmable Monitoring Coprocessor,&#8221;\u00a0in IEEE Computer Architecture Letters, vol. 17, no. 1, pp. 92-95, 1 Jan.-June 2018.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/hw-monitors-cal-2018.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2017<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[AIPR 2017]<\/strong> M. Louis, M. Alosco, B. Rowland, H. Liao, J. Wang, I. Koerte, M. Shenton, R. Stern, A. Joshi and A. Lin, &#8220;<span>Using Machine Learning Techniques for Identification of Chronic Traumatic Encephalopathy Related Spectroscopic Biomarkers<\/span>,&#8221; in Proc.\u00a0<span>Applied Imagery Pattern Recognition Workshop<\/span> on Big Data, Analytics and Beyond 2017. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/cte-aipr-2018.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HPEC 2017]<\/strong> B. Zhou, M. Egele and A. Joshi, &#8220;High-Performance Low-Energy Implementation of Cryptographic Algorithms on a Programmable SoC for IoT Devices,&#8221; in IEEE High Performance Extreme Computing Conference 2017. <span><a href=\"http:\/\/people.bu.edu\/joshi\/files\/fpga-enc.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/tcad-optical-2016.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[RIVER 2017]<\/strong> T. Zhang, J. Klamkin, A. Joshi and A. Coskun, &#8220;Thermal Management of Silicon Photonic NoCs in Many-core Systems,&#8221; in Optical Interconnect for Computing Systems, River Publishers 2017. <a href=\"http:\/\/www.riverpublishers.com\/book_details.php?book_id=331\">(link)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TCAD 2017]<\/strong>\u00a0<span>J.\u00a0Abell\u00e1n, A. Coskun, A. Gu, W. Jin, A. Joshi, A. Kahng, J. Klamkin, C. Morales, J. Recchio, V. Srinivas and T. Zhang*, &#8220;Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation&#8221; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no.5, pp.801-814, May 2017.\u00a0<\/span>(<strong>*Lead Author<\/strong>)<span>\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/tcad-optical-2017.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/tcad-optical-2016.pdf\">(pdf)<\/a>\u00a0<\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2017]<\/strong>\u00a0L. Delshadtehrani, J. Appavoo, M. Egele, A. Joshi and S. Eldridge, \u201cVaranus: An Infrastructure for Programmable Hardware Monitoring Units,\u201d Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2017.\u00a0<span><a href=\"http:\/\/people.bu.edu\/joshi\/files\/varanus-barc2017.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/tcad-optical-2016.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2017]<\/strong>\u00a0Z. Takhirov, J. Wang, V. Saligrama and A. Joshi, \u201cEnergy-Efficient Classification: Adaptive Approach,\u201d Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2017.\u00a0<span><a href=\"http:\/\/people.bu.edu\/joshi\/files\/BARC2017_paper_6.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/tcad-optical-2016.pdf\">(pdf)<\/a><\/span><\/li>\n<\/ul>\n<h3>2016<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[TACO 2016]<\/strong> A. Ziabari, Y. Sun, Y. Ma, D. Schaa, J. Abellan, R. Ubal, J. Kim, A. Joshi and D. Kaeli, &#8220;UMH: A Hardware-based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs,&#8221; <span>ACM<\/span><span>\u00a0Transactions on Architecture and Code Optimization vol. 13, no. 4 December 2016. <a href=\"http:\/\/people.bu.edu\/joshi\/files\/a35-ziabari.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/a35-ziabari.pdf\">(pdf)<\/a><\/span><\/li>\n<li style=\"text-align: justify;\"><strong>[JETC 2016]<\/strong> J.\u00a0Abell\u00e1n, C. Chen and A. Joshi, &#8220;<span>Electro-Photonic NoC Designs for Kilocore Systems,<\/span>&#8221; ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13, no. 2, November 2016.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/a24-abellan.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/a24-abellan.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISLPED 2016]<\/strong>\u00a0Z. Takhirov, J. Wang, V. Saligrama and A. Joshi, &#8220;Energy-Efficient Adaptive Classifier Design for Mobile Systems,&#8221; Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2016.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-ISLPED-2016.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-ISLPED-2016.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2016]<\/strong>\u00a0A. Coskun, A. Gu*, W. Jin, A. Joshi, A. B. Kahng, J. Klamkin, Y. Ma, J. Recchio*, V. Srinivas* and T. Zhang, &#8220;Cross-Layer Floorplan Optimization For Silicon Photonic NoCs In Many-Core Systems&#8221;, Proc. Design, Automation and Test in Europe (DATE) 2016.\u00a0(<strong>*Lead Authors<\/strong>)\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Photo_NoC_DATE_2016.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Photo_NoC_DATE_2016.pdf\">(pdf)\u00a0<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2016]<\/strong>\u00a0M. Zangeneh and A. Joshi, &#8220;Designing Tunable Sub-threshold Logic Circuits using Adaptive Feedback Equalization&#8221;\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 3, pp. 884-896, March 2016.<em>\u00a0<\/em><a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zanganeh_TVLSI_2016.pdf\">(pdf)<\/a><em>.<\/em><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2016]<\/strong>\u00a0S. Eldridge, T. Unger, M. Louis, A. Waterland, M. Seltzer, J. Appavoo and A. Joshi, &#8220;Neural Networks as Function Primitives: Software\/Hardware Support with X\u00adFILES\/DANA,&#8221; Proc.\u00a0Boston area ARChitecture (BARC) Workshop 2016.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/eldridge_barc2016.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/eldridge_barc2016.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2015<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[PACT 2015]<\/strong>\u00a0S. Eldridge, A. Waterland, M. Seltzer, J. Appavoo and A. Joshi, &#8220;Towards General-Purpose Neural Network Computing,&#8221; Proc.\u00a0Parallel Architectures and Compilation Techniques (PACT) 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/pact2015-eldridge.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/pact2015-eldridge.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[FIO 2015]<\/strong>\u00a0R. Adato, A. Uyar, M. Zangeneh, B. Zhou,\u00a0A. Joshi,\u00a0B. Goldberg and M. Selim Unlu, \u201cIntegrated\u00a0Nanoantenna Labels for Rapid Security Testing of Semiconductor Circuits,\u201d Proc.\u00a0Frontiers\u00a0in Optics\u00a02015.<\/li>\n<li style=\"text-align: justify;\"><strong>[NOCS 2015]<\/strong>\u00a0A. Ziabari, J. Abell\u00e1n, Y. Ma, A. Joshi and D. Kaeli, &#8220;Asymmetric NoC Architectures for GPU Systems,&#8221; Proc. International Symposium on Networks-on-Chip (NOCS) 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Ziabari_NOCS_2015.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Ziabari_NOCS_2015.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DAC 2015]<\/strong>\u00a0B. Zhou, R. Adato, M. Zangeneh, T. Yang, A. Uyar, B. Goldberg, M. Selim Unlu and A. Joshi, &#8220;Detecting Hardware Trojans Using Backside Optical Imaging of Embedded Watermarks,&#8221; Proc. Design Automation Conference (DAC) 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhou_DAC_2015.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Zhou_DAC_2015.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TCAD 2015]<\/strong>\u00a0C. Chen, J.\u00a0Abell\u00e1n\u00a0and A. Joshi, &#8220;Managing Laser Power in Silicon-Photonic NoC through Cache and NoC Reconfiguration,&#8221;\u00a0IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, no.6, pp.972-985, June 2015\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Chen_TCAD_2015.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ICS 2015]<\/strong>\u00a0A.\u00a0Ziabari, J. Abell\u00e1n, R. Ubal, C. Chen, A. Joshi and D. Kaeli, &#8220;Leveraging Silicon-Photonic NoC for Designing Scalable GPUs,&#8221; Proc. International Conference on Supercomputing (ICS) 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Ziabari_ICS_2015.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Ziabari_ICS_2015.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2015]<\/strong>\u00a0T. Cilingiroglu, M. Zangeneh, A. Uyar, W. Clem Karl, J. Konrad, A. Joshi, B. Goldberg and M. Selim Unlu, &#8220;Dictionary-based Sparse Representation for Resolution Improvement in Laser Voltage Imaging of CMOS Integrated Circuits,&#8221; Proc. Design, Automation and Test in Europe (DATE) 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Berkin_DATE_2015.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Berkin_DATE_2015.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BARC 2015]<\/strong>\u00a0S. Eldridge and A. Joshi, &#8220;Exploiting Hidden Layer Modular Redundancy for Fault-Tolerance in Neural Network Accelerators,&#8221; Proc. Boston area ARChitecture (BARC) Workshop 2015.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Eldridge_BARC_2015.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Eldridge_BARC_2015.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2014<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[NOCS 2014]<\/strong>\u00a0C. Chen, T. Zhang, P. Contu, J. Klamkin, A. Coskun, and A. Joshi, &#8220;Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs,&#8221; Proc. International Symposium on Networks-on-Chip (NOCS) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Chen_NOCS_2014.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2014]<\/strong>\u00a0M. Zangeneh and A. Joshi, &#8220;Design and Optimization of Nonvolatile Multi-bit 1T1R Resistive RAM,&#8221;\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems,\u00a0vol.22, no.8, pp.1815-1828, Aug. 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zangeneh_TVLSI_2014.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ALR 2014]<\/strong>\u00a0F.\u00a0Raudies, S. Eldridge, A. Joshi and M. Versace, &#8220;Learning to navigate in a virtual world using optic flow and stereo disparity signals,&#8221;\u00a0Artificial Life and Robotics,\u00a0Springer Japan\u00a0Aug. 2014.\u00a0<a href=\"http:\/\/link.springer.com\/article\/10.1007\/s10015-014-0153-1\">(link)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[NEUROARCH-ISCA 2014]<\/strong>\u00a0J. Appavoo, A. Waterland, S. Eldridge, K. Zhao, A. Joshi, S. Homer and M. Seltzer,\u00a0&#8220;Programmable Smart Machines: A Hybrid Neuromorphic approach to General Purpose Computation&#8221;\u00a0Neuromorphic Architectures Workshop (NeuroArch) held in conjunction with 41th International Symposium on Computer Architecture (ISCA-41) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/appavoo-neuroarch-2014.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/appavoo-neuroarch-2014.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[GLSVLSI 2014]<\/strong>\u00a0S. Eldridge, F. Raudies, D. Zou and A. Joshi, &#8220;Neural Network-Based Accelerators for Transcendental Function Approximation,&#8221; Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/glsvlsi2014-eldridge.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/glsvlsi2014-eldridge.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2014]\u00a0<\/strong>M. Zangeneh and A. Joshi, &#8220;Sub-threshold Logic Circuit Design using Feedback\u00a0Equalization,&#8221; Proc. Design, Automation and Test in Europe (DATE) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zangeneh_DATE_2014.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Zangeneh_DATE_2014.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DATE 2014]<\/strong>\u00a0T. Zhang, J.\u00a0Abell\u00e1n, A. Joshi and A. Coskun, &#8220;Thermal Management of Manycore Systems with\u00a0Silicon-Photonic Networks,&#8221; Proc. Design, Automation and Test in Europe (DATE) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhang_DATE_2014.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Zhang_DATE_2014.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SHAW-HPCA 2014]<\/strong>\u00a0C. Chen, A. Joshi and E. Salminen, \u201cProfiling EEMBC MultiBench Programs using Full-system Simulations,\u201d Proc. Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW) held in conjunction with 20th International Symposium On High Performance Computer Architecture (HPCA) 2014.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Chao_Shaw_Hpca_2014.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Chao_Shaw_Hpca_2014.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3 style=\"text-align: justify;\">2013<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ISLPED 2013]<\/strong>\u00a0Z. Takhirov, B. Nazer and A. Joshi, &#8220;Energy-Efficient Pass-Transistor-Logic Using Decision Feedback Equalization,&#8221; Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2013.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov_ISLPED2013.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov_ISLPED2013.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[BIC-ISCA 2013]\u00a0<\/strong>S. Eldridge, F. Raudies and A. Joshi, &#8220;Approximate Computation using Neuralized FPU,&#8221;\u00a0Brain-Inspired Computing (BIC) Workshop held in conjunction with 40th International Symposium on Computer Architecture (ISCA-40) 2013.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/approx-fpu-bic2013.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/approx-fpu-bic2013.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SPRINGER 2013]<\/strong>\u00a0C. Batten, A. Joshi, V. Stojanovi\u0107, and K. Asanovi\u0107, &#8220;Designing Nanophotonic Interconnection Networks,&#8221; in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Springer, 2013.\u00a0<a href=\"http:\/\/link.springer.com\/chapter\/10.1007\/978-1-4419-6193-8_3\">(link)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[JSTQE 2013]<\/strong>\u00a0C. Chen and A. Joshi, &#8220;Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture,&#8221;\u00a0IEEE Journal of Selected Topics in Quantum Electronics, vol.19, no.2, pp.338-350, March-April 2013.\u00a0<strong>(Invited paper)<\/strong>\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Chen_JSTQE_2013.pdf\">(pdf)<\/a><strong> <\/strong><\/li>\n<li style=\"text-align: justify;\"><strong>[BU 2013]\u00a0<\/strong>F. Raudies, S. Eldridge, A. Joshi and M. Versace, &#8220;Reinforcement Learning of Visual Navigation Using Distances Extracted from Stereo Disparity or Optic Flow&#8221; (Boston University\u00a0ECE-2013-1).\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/TechReportNo-ECE-2013-1-LearningVisualNavigation.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2012<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[LGDMA-IGCC 2012]<\/strong>\u00a0A. Joshi, C. Chen, Z. Takhirov and B. Nazer, &#8220;A Multi-layer Approach to Green Computing: Designing Energy-efficient Digital Circuits and Manycore Architectures,&#8221; Proc. Workshop on\u00a0Lighter-than-Green Dependable Multicore Architectures (LGDMA) held in conjunction with International Green Computing Conference (IGCC) 2012.\u00a0<strong>(Invited paper)\u00a0<\/strong><a href=\"http:\/\/people.bu.edu\/joshi\/files\/Joshi_Green_LGDMA_2012.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Joshi_Green_LGDMA_2012.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2012]<\/strong>\u00a0Z. Wang, M. Karpovsky and A. Joshi, &#8220;Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories,&#8221;\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.7, pp.1221-1234, July 2012.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Wang_NAND_TVLSI_2012.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[JETCAS 2012]<\/strong>\u00a0C. Batten, A. Joshi, V. Stojanovic, and K. Asanovic, &#8220;Designing Chip-Level Nanophotonic Interconnection Networks,&#8221; IEEE Journal on\u00a0Emerging and Selected Topics in Circuits and Systems, vol.2, no.2, pp.137-153, June 2012.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/JETCAS_2012.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2012]<\/strong>\u00a0Z. Wang, M. Karpovsky and A. Joshi, &#8220;Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes,&#8221;\u00a0IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, no.6, pp.1036-1048, June 2012.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Wang_Multiplier_TVLSI_2012.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ICCNS 2012]<\/strong>\u00a0M. Motter, M. Versace, and A. Joshi, &#8220;Neuromorphic solutions for UAS collision avoidance,&#8221; Proc. International Conference on Cognitive and Neural Systems (ICCNS) 2012.<\/li>\n<li style=\"text-align: justify;\"><strong>[GLSVLSI 2012]<\/strong>\u00a0M. Zangeneh and A. Joshi, &#8220;Performance and Energy Models for Memristor-based1T1R RRAM Cell,&#8221; Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2012.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Zangeneh_GLSVLSI2010.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Zangeneh_GLSVLSI2010.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ISQED 2012]<\/strong>\u00a0Z. Takhirov, B. Nazer and A. Joshi,\u00a0\u201cError Mitigation in Digital Logic using Feedback Equalization with Schmitt Trigger (FEST) Circuit,\u201d Proc. International Symposium on Quality Electronic Design (ISQED) 2012.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-isqed2012.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-isqed2012.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2011<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ALLERTON 2011]<\/strong>\u00a0Z. Takhirov, B. Nazer and A. Joshi,\u00a0\u201cA Preliminary Look at Error Avoidance in Digital Logic Via Feedback Equalization,\u201d in Proc. Allerton-11 2011.\u00a0<strong>(Invited paper)\u00a0<\/strong><a href=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-allerton2011.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov-allerton2011.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HOTI 2011]<\/strong>\u00a0C. Chen, J. Meng, A. Coskun and A. Joshi, \u201cExpress Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems,\u201d \u00a0in Proc. High-Performance Interconnects (HOTI) 2011.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Chen-hoti2011.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Chen-hoti2011.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[GLSVLSI 2011]<\/strong>\u00a0Z. Wang, M. Karpovsky and A. Joshi, \u201cInfluence of Metallic Tubes on the Reliability of CNTFET SRAMs: Error Mechanisms and Countermeasures,\u201d Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/gls088-wang.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/gls088-wang.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[GLSVLSI 2011]<\/strong>\u00a0J. Meng, C. Chen, A. Coskun and A. Joshi, \u201cRun-Time Energy Management of Manycore Systems Through Reconfigurable Interconnects,\u201d Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/meng_GLSVLSI11.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/meng_GLSVLSI11.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2010<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ISCA 2010]<\/strong>\u00a0S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic, K. Asanovic, \u201cRe- Architecting a DRAM Memory Channel with Monolithically Integrated Silicon Photonics,\u201d Proc. International Symposium on Computer Architecture (ISCA) 2010\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/photo-dram-isca2010-published.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/photo-dram-isca2010-published.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[DSN 2010]<\/strong>\u00a0Z. Wang, M. Karpovsky, A. Joshi, \u201cReliable MLC NAND Flash Memories Based on nonlinear t-Error-Correcting Codes\u201d, Proc. 40th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks (DSN), 2010\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/dsn2010-published.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/dsn2010-published.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[OFC 2010]<\/strong>\u00a0V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen, and K. Asanovic, \u201cDesign-space exploration for CMOS photonic processor networks,\u201d Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC\/NFOEC) , vol., no., pp.1-3, 21-25 March 2010\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Stojanovic2010OFC.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Stojanovic2010OFC.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[WTM 2010]<\/strong>\u00a0V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen and K. Asanovic, &#8220;CMOS photonic processor-memory networks,&#8221; Photonics Society Winter Topicals Meeting Series (WTM), 2010 IEEE , vol., no., pp.118-119, 11-13 Jan. 2010\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Stojanovic2010Wtc.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Stojanovic2010Wtc.pdf\">(pdf)<\/a><\/li>\n<\/ul>\n<h3>2009<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[ICICSP 2009]<\/strong>\u00a0Z. Wang, M. Karpovsky, B. Sunar, and A. Joshi, &#8220;Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes,&#8221; Proc. Int. Conf. on Information, Communications and Signal Processing, Dec. 2009\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/icics09.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/icics09.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[UC BERKELEY 2009]<\/strong>\u00a0S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and K. Asanovic, \u201cRe-architecting DRAM with Monolithically Integrated Silicon Photonics\u201d (UC Berkeley EECS-2009-179).\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/EECS-2009-179.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[PICA-MICRO 2009]<\/strong>\u00a0A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, &#8220;Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics&#8221; Proc. Workshop on Photonic Interconnects &amp; Computer Architecture (PICA) held in conjunction with 42nd Annual ACM\/IEEE International Symposium on Microarchitecture, MICRO-42 2009<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Pica2009_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Pica2009_Ajay_Joshi.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[LEOS 2009]<\/strong>\u00a0A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, &#8220;Designing Manycore Processor Networks using Silicon Photonics,&#8221; Proc. IEEE\/Photonics Society Annual Meeting 2009.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/photonic-on-off-chip-leos2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/photonic-on-off-chip-leos2009.pdf\">\u00a0(pdf)<\/a><\/li>\n<\/ul>\n<h3>Before\u00a0September 2009<\/h3>\n<ul>\n<li style=\"text-align: justify;\"><strong>[HOTI 2009]<\/strong>\u00a0A. Joshi, B. Kim and V. Stojanovic, &#8220;Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects,&#8221; Proc. IEEE Symposium on High-Performance Interconnects, Aug 2009.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/eq-topo-comp-hoti2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/eq-topo-comp-hoti2009.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[MICRO 2009]<\/strong>\u00a0C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, &#8220;Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,&#8221;\u00a0<em>Micro, IEEE<\/em>\u00a0, vol.29, no.4, pp.8-21, July-Aug. 2009.\u00a0<strong>(IEEE Micro Special Issue:\u00a0Micro&#8217;s Top Picks from Hot Interconnects 16)<\/strong>\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/micr-29-04-batt.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/micr-29-04-batt.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[ICS 2009]<\/strong>\u00a0S. Beamer, K. Asanovi\u0107, C. Batten, A. Joshi, and V. Stojanovi\u0107, &#8220;Designing Multi-socket Systems Using Silicon Photonics&#8221;, Proc. 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, NY, June 2009.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/multi-socket-ics-2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/multi-socket-ics-2009.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[CLEO 2009]<\/strong>\u00a0V. Stojanovic, A. Joshi, C. Batten, J. Kwon and K. Asanovic, &#8220;Manycore Processor Networks with Monolithic Integrated CMOS Photonics,&#8221; Proc. CLEO 2009\u00a0<strong>(Invited paper)<\/strong><a href=\"http:\/\/people.bu.edu\/joshi\/files\/photo-net-cleo-2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/photo-net-cleo-2009.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[NOCS 2009]<\/strong>\u00a0A. Joshi, F. Chen and V. Stojanovic, &#8220;A Modeling and Exploration Framework for Interconnect Network Design in the Nanometer Era,&#8221; 3rd IEEE\/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/cnt-nocs-2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/cnt-nocs-2009.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[NOCS 2009]<\/strong>\u00a0A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, &#8220;Silicon-Photonic Clos Networks for Global On-Chip Communication,&#8221; 3rd IEEE\/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009\u00a0<strong>(Nominated for Best Paper Award)<\/strong>.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/photo-clos-nocs2009.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/photo-clos-nocs2009.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[HOTI 2008]<\/strong>\u00a0C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, &#8220;Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics&#8221;, Proc. 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, CA, August 2008.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Hoti_2008_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Hoti_2008_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2007]<\/strong>\u00a0A. Joshi, G. Lopez and J. Davis, &#8220;Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing,&#8221;\u00a0Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, no.9, pp.990-1002, Sept. 2007.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/TVLSI_2007_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/TVLSI_2007_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[NANONETS 2007]<\/strong>\u00a0F. Chen, A. Joshi, V. Stojanovic and A. Chandrakasan, &#8220;Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,&#8221; Proc. Nanonets 2007.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/Nanonets_2007_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/Nanonets_2007_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[IITC 2006]<\/strong>\u00a0D. Sekar, R. Venkatesan, K. Bowman, A. Joshi, J. Davis and J. Meindl, &#8220;Optimal repeaters for sub-50nm interconnect networks,&#8221; Proc. IITC 2006, pp. 199-201.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/IITC_2006_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/IITC_2006_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[VLSI Design 2006]<\/strong>\u00a0A. Joshi, V. Deodhar and J. Davis, &#8220;Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing,&#8221; Proc. VLSI Design 2006, pp. 773-776.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/VLSI_2006_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/VLSI_2006_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[TVLSI 2005]<\/strong>\u00a0A. Joshi and J. Davis, &#8220;Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI),&#8221;\u00a0IEEE Transactions on\u00a0Very Large Scale Integration (VLSI) Systems, vol.13, no.8, pp.899-910, Aug. 2005.\u00a0<a href=\"http:\/\/people.bu.edu\/joshi\/files\/TVLSI_2005_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/TVLSI_2005_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[AMC 2005]<\/strong>\u00a0J. Davis, V. Deodhar and A. Joshi, &#8220;The Impact of Wave Pipelining on Future Interconnect Technologies,&#8221; Proc. AMC 2005\u00a0<strong>(Invited paper)<\/strong>.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/AMC_2005_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/AMC_2005_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SOCC 2005]<\/strong>\u00a0A. Joshi and J. Davis, &#8220;Gigascale ASIC\/SoC Design using Wave-Pipelined Multiplexed (WPM) Routing,&#8221; Proc. IEEE-SOCC 2005, pp. 139-142.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/SOCC_2005_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/SOCC_2005_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[GLSVLSI 2005]<\/strong>\u00a0A. Joshi and J. Davis, &#8220;Wave-Pipelined 2-Slot Time Division Multiplexed (WP\/2-TDM) Routing,&#8221; Proc. GLSVLSI 2005, pp.446-451.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/GLSVLSI_2005_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/GLSVLSI_2005_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\"><strong>[SLIP 2004]<\/strong>\u00a0A. Joshi and J. Davis, &#8220;A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI),&#8221; Proc. IEEE\/ACM SLIP Workshop 2004, pp. 64-68.<a href=\"http:\/\/people.bu.edu\/joshi\/files\/SLIP_2004_Ajay_Joshi.pdf\" title=\"http:\/\/people.bu.edu\/joshi\/files\/SLIP_2004_Ajay_Joshi.pdf\">\u00a0(pdf)<\/a><\/li>\n<\/ul>\n<h3>PhD Thesis<\/h3>\n<ol>\n<li style=\"text-align: justify;\">Cansu Demirkiran, &#8220;Building Next-Generation Deep Learning Hardware Using Photonic Computing,&#8221; August 2024.<\/li>\n<li style=\"text-align: justify;\">Zahra Azad, &#8220;On designing hardware accelerator-based systems: interfaces, taxes and benefits,&#8221; March 2023.<\/li>\n<li style=\"text-align: justify;\">Rashmi Agrawal, &#8220;Hardware accelerators for post-quantum cryptography and fully homomorphic encryption,&#8221; November 2022.<\/li>\n<li style=\"text-align: justify;\">Marcia Sahaya Louis, &#8220;Machine Learning for Magnetic Resonance Spectroscopy: Modeling in the Pre-clinical Development Process,&#8221; June 2022.<\/li>\n<li style=\"text-align: justify;\">Sadullah Canakci, &#8220;Directing Greybox Fuzzing to Discover Bugs in Hardware and Software,&#8221; March 2022.<\/li>\n<li style=\"text-align: justify;\">Furkan Eris, &#8220;Leveraging Machine Learning for Hardware Design and Optimization,&#8221; March 2022.<\/li>\n<li style=\"text-align: justify;\">Aditya Narayan, &#8220;<span>Energy-efficient architectures for chip-scale networks and memory systems using silicon-photonics technology<\/span>,&#8221; April 2021 <a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Narayan_PhD_Thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Leila Delshadtehrani, &#8220;<span>Enabling Software Security Mechanisms Through Architectural Support<\/span>,&#8221; March 2021\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Delshadtehrani_PhD_Thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Saiful Mojumder, &#8220;True Shared Memory Architecture for Next-Generation Multi-GPU Systems,&#8221; February 2021 <a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Mojumder_PhD_Thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Yenai Ma, &#8220;Cross-Layer Design of Thermally-Aware 2.5D Systems,&#8221; May 2020. <a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Ma_PhD_Thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Boyou Zhou, &#8220;A Multi-layer Approach to Designing Secure Systems: From Circuit to Software,&#8221; March 2019.\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhou_PhD_Thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Zafar Takhirov, &#8220;Designing Energy-efficient Computing Systems Using Equalization and Machine Learning,&#8221; September 2017. <a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Takhirov_PhD_thesis.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Schuyler Eldridge, &#8220;Neural Network Computing using On-chip Accelerators,&#8221; August 2016.\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/thesis-eldridge.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Mahmoud Zangeneh, &#8220;Designing Energy-efficient Sub-threshold Logic Circuits using Equalization and Non-volatile Memory Circuits using Memristors,&#8221; March 2015\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/Mahmoud_Zangeneh_Thesis_Final.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Mahmoud_Zangeneh_Thesis_Final.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Chao Chen, &#8220;Energy-efficient Electrical and Silicon-photonic Networks in Manycore Systems,&#8221; April 2014\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/Chao_Chen_Thesis_Final.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Chao_Chen_Thesis_Final.pdf\">(pdf)<\/a><\/li>\n<li style=\"text-align: justify;\">Zhen Wang, &#8220;Nonlinear Robust Codes and their Applications for Design of Reliable and Secure Devices,&#8221; April 2011\u00a0<a title=\"http:\/\/people.bu.edu\/joshi\/files\/Zhen_Wang_Thesis_Final.pdf\" href=\"http:\/\/people.bu.edu\/joshi\/files\/Zhen_Wang_Thesis_Final.pdf\">(pdf)<\/a><\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"<p>2026 [EURO-PAR 2026]\u00a0S. Guzelhan, F. Acun, C. Hankendi, A. Coskun, and A. Joshi, &#8220;Privacy-Preserving Data Center Demand Response Participation using Multi-Party Computation,&#8221; to appear in International European Conference on Parallel and Distributed Computing (Euro-Par) 2026. [JETC 2026] F. Fayza, C. Demirkiran, G. Yang, H. Chen, C-K. Liu, A. Mohan, H. Errahmouni, S. Yun, M. Imani, [&hellip;]<\/p>\n","protected":false},"author":4654,"featured_media":0,"parent":0,"menu_order":6,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/pages\/42"}],"collection":[{"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/users\/4654"}],"replies":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/comments?post=42"}],"version-history":[{"count":50,"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/pages\/42\/revisions"}],"predecessor-version":[{"id":1692,"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/pages\/42\/revisions\/1692"}],"wp:attachment":[{"href":"https:\/\/www.bu.edu\/icas\/wp-json\/wp\/v2\/media?parent=42"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}