• Starts: 12:30 pm on Wednesday, December 4, 2024
  • Ends: 2:30 pm on Wednesday, December 4, 2024

ECE PhD Thesis Defense: Zaid Tahir

Title: FLEXIBLE SECURE COMMUNICATION PRIMITIVES FOR DIVERSE DEPLOYMENT SCENARIOS OF HARDWARE OPERATING SYSTEMS FOR FPGAS

Presenter: Zaid Tahir

Advisor: Professor Martin Herbordt

Chair: Professor Tianyu Wang

Committee: Professor Martin Herbordt, Professor Richard West, Professor Gianluca Stringhini, Professor Osama Alshaykh, Dr. Ahmed Sanaullah

Google Scholar Link: https://scholar.google.com/citations?user=NoqDG1EAAAAJ&hl=en

Abstract: Communication capabilities of FPGAs combined with flexibility in hardware (re-configurable logic) and software (soft-processors), provide FPGAs a competitive edge over alternate technologies where communication requirements are highly demanding. The problem lies in not being able to harness these capabilities efficiently due to the fact that in the current FPGA hardware-development ecosystem, entire hardware stacks have to be rebuilt or reworked, even for minor changes in the application or target device. Existing frameworks like FPGA-based NICs or hardware OS (hOS) shells reduce development complexity by connecting IP blocks needed to support core functionality, but the limitation with these shells is that they have tightly coupled IP blocks, fixed overheads, unique interfaces, vendor-specific IP and devices, requiring custom host-side drivers, libraries and are limited to certain configurations.

In this thesis we explore hardware architectures, design decisions, and techniques in order to generate flexible secure communication primitives as a part of developing a loosely-coupled vendor-agnostic hOS generator. A few of these communication primitives include the network subsystem, PCIe subsystem, flexible intra-subsystem communication implemented using soft-processors and memory subsystems with arbitration, etc. This dissertation validates the thesis that developing such highly configurable communication primitives for hOS generators saves FPGA resources and reduces implementation efforts whether it involves porting to different devices or targeting various configurations.

The first contribution of this thesis is developing a highly configurable and parameterized open-source network communication primitives and integrating it into our vendor-agnostichOS generator (DISL), where users of DISL can use a single configuration script to generate various configurations of network subsystems by selecting required modules from different PHYs, MACs, MIIs, Ethernet/Network/Transport layer blocks, interfaces, target configurations, DMA and memory devices, interconnects and arbitration options. We have also developed an extensive C library for network subsystem M-plane control using RISC-V.

Our second contribution involves the security and routing of the hOS communication primitives for which we have developed an eBPF ISA compliant CPU core called VeBPF (Verilog eBPF). We have developed a novel many-core framework using this VeBPF core as the PE (Processing Element) to implement eBPF rules for network firewall and routing, optimized for low resource usage for IoT target configurations.

As our third major contribution, we have developed a heterogeneous simulation framework for the network subsystem using Python, Cocotb, Icarus Verilog and GTK-WAVE for simulating complex network packet interactions with the various subsystems of DISL and external applications. We have also developed an automatic testing framework for development and further advancement of the VeBPF CPU core. We have implemented C libraries for real-time debugging of the packet processing, and we provide directions on using existing SDK for live debugging of network packets.

We demonstrate the flexibility, portability of the developed communication primitives by porting the network communication primitives to different FPGA boards with different PHYs, MIIs, MACs, interfaces and throughput, using a single configuration script in DISL and setting up eBPF rules for network packet processing in different FPGAs using the VeBPF many-core architecture.

Location:
PHO 339