{"id":41058,"date":"2024-06-27T14:16:52","date_gmt":"2024-06-27T18:16:52","guid":{"rendered":"https:\/\/www.bu.edu\/cise\/?p=41058"},"modified":"2024-06-27T14:38:46","modified_gmt":"2024-06-27T18:38:46","slug":"coskun-lab-collaborates-with-brown-university-researchers-on-breakthrough-in-chip-thermal-simulation","status":"publish","type":"post","link":"https:\/\/www.bu.edu\/cise\/coskun-lab-collaborates-with-brown-university-researchers-on-breakthrough-in-chip-thermal-simulation\/","title":{"rendered":"Coskun Lab Collaborates with Brown University Researchers on Breakthrough in Chip Thermal Simulation"},"content":{"rendered":"<p><span style=\"color: #000000;\"><strong><i>Ay\u015fe Co\u015fkun<\/i><i> and co-authors win prestigious TCAD Best Paper Award for research advancements in fast chip thermal simulation<\/i><\/strong><\/span><\/p>\n<p><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">Boston, MA, June 27, 2024 &#8211; BU Electrical and Computer Engineering (ECE) Professor and Center for Information and Systems Engineering (CISE) Director, <\/span><span style=\"font-weight: 400;\">Ay\u015fe Co\u015fkun<\/span><span style=\"font-weight: 400;\">, Professor Sherief Reda of Brown University, three BU alumni Zihao Yuan (CE PhD&#8217;22), Prachi Shukla (CE PhD&#8217;22), and Sean Nemtzow (CE BS&#8217;21), and Sofiane Chetoui (PhD\u201922 from Brown) were recognized for their outstanding contributions to the field of electronic design automation with the <a href=\"https:\/\/ieee-ceda.org\/awards\/donald-o-pederson-award#recipients\" target=\"_blank\" rel=\"noopener noreferrer\">2024 TCAD Donald O. Pederson Best Paper Award<\/a><\/span><span style=\"font-weight: 400;\">.\u00a0<\/span><\/span><\/p>\n<p><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">The paper, <a href=\"https:\/\/www.bu.edu\/peaclab\/files\/2024\/02\/PACT_An_Extensible_Parallel_Thermal_Simulator_for_Emerging_Integration_and_Cooling_Technologies.pdf\" target=\"_blank\" rel=\"noopener noreferrer\">&#8220;PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies,&#8221;<\/a><\/span><span style=\"font-weight: 400;\">\u00a0was published in <\/span><i><span style=\"font-weight: 400;\">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/span><\/i><span style=\"font-weight: 400;\"> 41(4), in April 2022. The award was presented at the annual Design Automation Conference (DAC) on June 27 in San Francisco, CA.<\/span><span style=\"font-weight: 400;\">\u00a0<\/span><\/span><\/p>\n<p><span style=\"color: #000000;\"><img loading=\"lazy\" src=\"\/cise\/files\/2024\/06\/TCADBPA0451-636x478.png\" alt=\"\" width=\"494\" height=\"371\" class=\"wp-image-41062 aligncenter\" srcset=\"https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451-636x478.png 636w, https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451-1024x770.png 1024w, https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451-768x577.png 768w, https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451-1536x1154.png 1536w, https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451-400x300.png 400w, https:\/\/www.bu.edu\/cise\/files\/2024\/06\/TCADBPA0451.png 1815w\" sizes=\"(max-width: 494px) 100vw, 494px\" \/><\/span><\/p>\n<p><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">The eponymous PACT, a groundbreaking <\/span><span style=\"font-weight: 400;\">parallel thermal simulator, is designed to help analyze computer chips and cooling technologies. It achieves remarkable speeds by combining compact thermal modeling with parallelization, simultaneously modeling heat and running a large number of calculations. Demonstrated by its use with OpenROAD (an end-to-end open-source silicon compiler), PACT enables smooth amalgamation with circuit design tools.\u00a0<\/span><\/span><\/p>\n<p><span style=\"font-weight: 400; color: #000000;\">PACT tackles the fragmentation, currently present in thermal modeling tools, by providing an inclusive solution involving standard-cell to architecture-level evaluations, supporting a variety of chip integration and cooling strategies. Its design ensures seamless adaptation to new cooling technologies, as validated in case studies on liquid, thermoelectric, and two-phase cooling systems.<\/span><\/p>\n<p><span style=\"font-weight: 400; color: #000000;\">As demonstrated by experimentation, PACT is a highly precise tool, exhibiting a comparable margin of error to that of other precision tools such as COMSOL. PACT is nearly 200 times faster than methodologies like HotSpot, a popular academic tool, especially when modeling dynamic conditions. PACT has garnered significant interest from industry as a top solution for thermal analysis in modern chip design because of its recognized speed, accuracy, and versatility.<\/span><\/p>\n<p><span style=\"color: #000000;\"><span style=\"font-weight: 400;\">\u201cPACT fills an important gap in chip thermal simulation by providing a fast, accurate, and open-source tool. Especially as chip design moves onto more complex integration technologies, such as 2.5D and 3D integration, existing methods do not provide the necessary speed and ease of use or extensibility. We hope to grow the PACT open-source community into a vibrant ecosystem and enable broader use in both academia and industry,\u201d says <\/span><span style=\"font-weight: 400;\">Co\u015fkun<\/span><span style=\"font-weight: 400;\">.<\/span><\/span><\/p>\n<p><span style=\"color: #000000;\"><b>About<\/b><\/span><br \/>\n<span style=\"color: #000000;\"><a href=\"https:\/\/www.bu.edu\/cise\/profile\/ayse-kivilcim-coskun\/\" style=\"color: #000000;\"><span style=\"font-weight: 400;\"><img loading=\"lazy\" src=\"\/cise\/files\/2020\/12\/Untitled-design-1-636x497.jpg\" alt=\"\" width=\"168\" height=\"132\" class=\"wp-image-30454 alignleft\" \/><a href=\"https:\/\/www.bu.edu\/cise\/profile\/ayse-kivilcim-coskun\/\" target=\"_blank\" rel=\"noopener noreferrer\">Ay\u015fe Co\u015fkun<\/a><\/span><\/a> <span style=\"font-weight: 400;\">is a Professor of Electrical and Computer Engineering at Boston University, Director of the Center for Information &amp; Systems Engineering <a href=\"http:\/\/bu.edu\/cise\" target=\"_blank\" rel=\"noopener noreferrer\">(CISE)<\/a><\/span><span style=\"font-weight: 400;\">, and leads the <\/span><span style=\"font-weight: 400;\">Performance and Energy Aware Computing Lab <a href=\"https:\/\/www.bu.edu\/peaclab\/\" target=\"_blank\" rel=\"noopener noreferrer\">(PEACLab)<\/a><\/span><span style=\"font-weight: 400;\">. Her accolades include the IBM Faculty Award in 2020, invited participation in the National Academy of Engineering Frontiers of Engineering Symposium in September 2019, and the IEEE CEDA Ernest S. Kuh Early Career Award in 2017.<\/span><\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Ay\u015fe Co\u015fkun and co-authors win prestigious TCAD Best Paper Award for research advancements in fast chip thermal simulation Boston, MA, June 27, 2024 &#8211; BU Electrical and Computer Engineering (ECE) Professor and Center for Information and Systems Engineering (CISE) Director, Ay\u015fe Co\u015fkun, Professor Sherief Reda of Brown University, three BU alumni Zihao Yuan (CE PhD&#8217;22), [&hellip;]<\/p>\n","protected":false},"author":22679,"featured_media":41070,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[26,127,77,1],"tags":[],"_links":{"self":[{"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/posts\/41058"}],"collection":[{"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/users\/22679"}],"replies":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/comments?post=41058"}],"version-history":[{"count":15,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/posts\/41058\/revisions"}],"predecessor-version":[{"id":41081,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/posts\/41058\/revisions\/41081"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/media\/41070"}],"wp:attachment":[{"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/media?parent=41058"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/categories?post=41058"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.bu.edu\/cise\/wp-json\/wp\/v2\/tags?post=41058"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}