ECE PhD Prospectus Defense: Mohammadamin Hajikhodaverdian

ECE PhD Prospectus Defense: Mohammadamin Hajikhodaverdian

Title: ML-accelerated Temperature-aware Design of 2.5D/3D AI Chips

Presenter: Mohammadamin Hajikhodaverdian

Advisor: Professor Ayse Coskun

Chair: Professor Ajay Joshi

Committee: Professor Ayse Coskun, Professor Ajay Joshi, Professor Sherief Reda, Professor Tali Moreshet.

Google Scholar Profile: https://scholar.google.com/citations?user=JKZ-_l8AAAAJ&hl=en

Abstract: Chiplet-based systems (2.5D/3D architectures) are emerging as key paths forward as transistor counts continue to rise and the conventional 2D scaling slows. These 2.5D/3D architectures, however, increase power density and limit heat removal, making temperature a critical constraint that affects performance, reliability, and energy efficiency. To address this, we need temperature-aware design-space exploration and the ability to quickly iterate over architectures, floorplans, and mappings, while considering these thermal limits. This goal can be achieved only by using a thermal simulator that is both fast and accurate, and that can fit within the inner loop of design-space exploration. However, conventional thermal simulators, such as finite-element-method (FEM)-based or compact thermal models (CTMs), remain expensive when repeatedly invoked at high resolution. This thesis argues that a lightweight, physically informed machine-learning thermal framework can deliver fast, high-fidelity simulation, making thermal-aware design optimization of emerging Monolithic 3D AI accelerators practical and scalable. To achieve this, we propose ML-PACT, a novel framework integrating CTMs with physics-informed ML. We introduce a window-based model-reduction technique for scalable steady-state analysis and a PCA-based framework for transient simulations. We utilize this framework to optimize two novel architectures: WS-MONO3D, a weight-stationary systolic array using vertical interconnects, and SPRATA, a pipelined ReRAM-based 3D accelerator for transformers. Our evaluations demonstrate significant reductions in EDP and improved thermal efficiency compared to 2D and GPU baselines. Future research will evolve ML-PACT into an end-to-end design workflow to enable thermal-aware architectural exploration for 3D-ICs.

When 1:00 pm - 2:30 pm on 2 February 2026
Building PHO 339