ECE PhD Prospectus Defense: Arman Tan

ECE PhD Prospectus Defense: Arman Tan

Title: Hardware Implementation of Energy-Efficient Mixed-Signal and Radio-Frequency Systems Assisted by Signal Processing Algorithms

Presenter: Arman Tan

Advisor: Professor Rabia Yazicigil

Chair: Professor Ajay Joshi

Committee: Professor Rabia Yazicigil, Professor Ajay Joshi, Professor David Starobinski, Dr. Gabriele Manganaro

Google Scholar Link: https://scholar.google.com/citations?user=m7WT2_gAAAAJ&hl=en

Abstract: Modern wireless communication systems demand increasingly higher power efficiency across both mixed-signal and RF domains. Transmitters must deliver high output power with minimal loss of efficiency during power back-off (PBO), while analog-to-digital converters (ADCs) must digitize high-input-range signals without consuming high power. To overcome these limitations, two promising architectural directions have gained interest. The first is the use of digital transmitter (DTx) architectures, where amplitude and phase modulations are implemented with digitally controlled switching architectures. Switched-capacitor power amplifiers (SCPAs) incorporated within polar or quadrature DTx topologies have demonstrated excellent energy scalability and high efficiency across power back-off levels. The second direction is modulo-sampling ADCs, which enable theoretically unlimited signal range by folding the input signal prior to quantization. This allows a low-power ADC core to process large-swing inputs without distortion while preserving full reconstructability of the original waveform. The first part of this work focuses on the design of the phase modulator and the digital back-end for a fully integrated optimal modulation digital transmitter (OMTx) implemented in 65nm CMOS. Measurement results demonstrate improved BER/SER performance for 64-point and 256-point optimal modulation without requiring any CORDIC-based baseband processing. The second part develops the theoretical foundations of a modulo-sampling ADC and circuit-level design of a modulo-sampling front-end, which enables a higher input signal voltage range by folding the input signal prior to quantization. The power bounds of the modulo-sampling ADC by comparing to conventional ADCs are investigated. To support practical hardware realization, a Modulo-Reset-to-Zero (MRZ) folding technique is introduced, providing robust threshold detection in the modulo-folding operation for data converter systems.

When 9:00 am - 10:30 am on 11 December 2025
Building PHO 339