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- ECE PhD Thesis Defense: Danchen Jia11:00 am
- Ni de Aquí, Ni de Allá (Not From Here, Not From There) Exhibition11:00 am
- How Setting Up Informational Interviews NOW will Advance Your Career LATER12:00 pm
- ECE PhD Prospectus Defense: Zeynep Ece Kizilates2:00 pm
- ECE PhD Thesis Defense: Daniel Shahar2:00 pm
- Employee Commuter Benefit Party4:00 pm
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- The Limits of "Mixedness": Ethno-National Conflicts in post-1948 Israel’s “Mixed Cities”4:30 pm
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- Directors' Project7:30 pm
- Crossing the Finish Line: Finalizing Your End-of-Semester Gradebook10:00 am
- Seminar Series: Theodore Greene (Bowdin College)12:00 pm
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- Fall Educational Policy Seminar: Melissa "Mimi" Arnold Lyon3:00 pm
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ECE PhD Prospectus Defense: Zeynep Ece Kizilates
ECE PhD Prospectus Defense: Zeynep Ece Kizilates
Title: Modular GRAND Architectures for Diverse Communication Channels and Applications
Presenter: Zeynep Ece Kizilates
Advisor: Professor Rabia Tugce Yazicigil
Chair: Professor Douglas Densmore
Committee: Professor Rabia Tugce Yazicigil, Professor Douglas Densmore, Professor Bobak Nazer, Professor Muriel Medard, Professor Ken R. Duffy.
Google Scholar Profile: https://scholar.google.com/citations?user=dU8vIGoAAAAJ&hl=en
Abstract: Error-correcting codes (ECCs) ensure reliable communication, but traditional decoders are tied to specific code structures, requiring separate hardware for each standard. The Guessing Random Additive Noise Decoding (GRAND) framework breaks this dependency by estimating channel noise with low architectural complexity. Building on this, several variants have extended GRAND to realistic wireless conditions, incorporating other features. However, these advances introduce new computational and architectural challenges. Addressing these challenges requires rethinking how GRAND algorithms can remain hardware-efficient as they evolve toward more application-specific purposes. This thesis develops a modular architectural framework for recent ORBGRAND-based decoders using fixed-point arithmetic, lightweight nonlinear approximations, and reusable compute units. Two silicon-proven designs demonstrate this approach: ORBGRAND-AI, which performs correlation-aware, modulation-adaptive soft-input computation, and SOGRAND, which enables accurate soft-output generation. Together, these architectures show that diverse GRAND-family algorithms can be supported within a unified, hardware-efficient foundation that maintains scalability and hardware efficiency.
| When | 2:00 pm - 3:30 pm on 9 December 2025 |
|---|---|
| Building | PHO 901 |