Hardware Security

Project Summary:

Cryptographic algorithms are designed so that by observing only the inputs and outputs of the algorithm it is computationally infeasible to break the cipher, or equivalently determine the secret key used in encryption and decryption. Thus, the algorithm itself does not leak enough useful information during its operation to compromise its security. However, when a physical implementation of the algorithm is considered, additional information like power consumption, behavior as a result of internal faults, and timing of the circuit implementing the algorithm can provide enough information to compromise the security of the system. This type of data can now be readily gathered since cryptographic hardware is accessible to anyone. (smart cards, SIM cards, USB tokens) Attacks based on the use of this implementation specific information are known as Side Channel Attacks (SCA). Contrary to traditional cryptanalysis attacks, examples show that a very small amount of side-channel information is enough to completely break a cryptosystem. The goal of the project is to develope methods and designs to make such attacks infeasable.

Robust DFA Resistant AES

(A Robust, DFA resistant FPGA implementaion of AES)

Project Components:

  • Application of Robust Codes to protect encryption hardware against Differential Fault Analysis (DFA) and natural soft errors.
  • Analysis and design of balanced dual rail asynchronous gates as a countermeasure against Simple Power Analysis (SPA) and Differential Power Analysis (DPA) of encryption hardware

Related Publications:

  • O. Keren, I. Levin, M. G. Karpovsky, “Duplication Based One-to-many Coding for Trojan HW Detection”, submitted to Int. Symp.on Defect and Fault Tolerance in VLSI Systems, 2010
  • Z. Wang, M. Karpovsky, “Robust FSMs for Cryptographic Devices Resilient to Strong Fault Injection Attacks” , Proc Int Symp. on On-line Tesing, July 2010
  • Z. Wang, M.G. Karpovsky, B.Sunar, A.Joshi, “Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes”, Proc. Int. Conf. on Information, Communications Security, Dec. 2009
  • Z. Wang, M. G. Karpovsky, B Sunar, “Multilinear Codes for Robust Error Detecrion”, Proc. Int. On-Line Testing Symp., June, 2009
  • K. Kulikowski, Z. Wang, M.G. Karpovsky, “Comparative Analysis of Fault Attack Resistant Architectures for Private and Public Key Cryptosystems”, Proc of Int. Workshop on Fault-tolerant Cryptographic Devices, 2008
  • K. Kulikowski, M. G. Karpovsky, A. Taubin, Z. Wang. “System-Level Concurrent Fault Detection for Secure QDI Asynchronous Circuits”. Proceedings of Workshop on Dependable and Secure Nanocomputing, DSN-08, 2008.
  • M.G.Karpovsky, K. Kulikowski, Z, Wang, “Robust Error Detection in Communication and Computation Channels”, Keynote paper, Int. Workshop on Spectral Techniques, 2007
  • Mark Karpovsky, Konrad J. Kulikowski, Zhen Wang. “On-line Self Error Detection with Equal Protection against All Errors”. International Journal of Highly Reliable Electronic System Design, 2008.
  • Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin. “Robust Codes and Robust, Fault Tolerant Architectures of the Advanced Encryption Standard”. Journal of Systems Architecture special issue on Embedded Cryptographic Hardware. vol. 53, pp. 138-139, 2007
  • Konrad J. Kulikowski, Alexander Smirnov, Alexander Taubin. “Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks”. Workshop on Cryptographic Hardware and Embedded Systems 2006 (CHES’06) Yokohama, Japan. October 2006.
  • Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin. “DPA on Faulty Cryptographic Hardware and Countermeasures”. Workshop on Fault Diagnosis and Tolerance in Cryptography 2006 (FDTC’06) Yokohama, Japan. October 2006.
  • Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin. “Power Attacks on Secure Hardware Based on Early Propagation of Data “. International On-Line Testing Symposium (IOLTS’06) Lake of Como, Italy, July 2006.
  • Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin , “Robust Codes for Fault Attack Resistant Cryptographic Hardware “, Workshop on Fault Diagnosis and Tolerance in Cryptography 2005 (FTDC’05), September 2005.
  • Daniel Jay MacDonald. “A Balanced-Power Domino-Style Standard Cell Library for Fine-Grain Asynchronous Pipelined Design to Resist Differential Power Analysis Attacks “. Master’s Thesis, 2005.
  • Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin, ” Memories with Robust Self Error Detection Invariant to Error Distributions”, In Informal Proceedings of the 10th European Test Symposium (ETS’05), May 2005.
  • Konrad J. Kulikowski, Ming Su, Alexander Smirnov, Alexander Taubin, Mark Karpovsky, and Daniel MacDonald, “Delay Insensitive Encoding and Power Analysis: A Balancing Act”, Proc. 11th Int. Symp. on Asynchronous Circuits and Systems (ASYNC’05), 2005
  • Mark Karpovsky and Alexander Taubin, “A New Class of Nonlinear Systematic Error Detecting Codes”, IEEE Trans Info Theory, Vol 50, No.8, 2004, pp.1818-1820
  • Mark Karpovsky, Konrad J. Kulikowski, and Alexander Taubin, ” Robust Protection Against Fault-Injection Attacks of Smart Cards Implementing the Advanced Encryption Standard”. T Proc. Int. Conference on Dependable Systems and Networks (DSN’04), July, 2004
  • Mark Karpovsky, Konrad J. Kulikowski, and Alexander Taubin, ” Differential Fault Analysis Attack Resistant Architectures for the Advanced Encryption Standard” . Proc. World Computing Congress, Cardis, Aug., 2004