# Publications

## Journal/Conference Publications

### 2014

P. Luo, A.Yu-Lun Lin, Z. Wang and M.G. Karpovsky, “Hardware Implementation of Reliable and Secure Shamir’s Secret Sharing Scheme”, *Proc. Int. Symp. On High Assurance Systems Engineering*, 2014.

M.G. Karpovsky, L. Levitin, M. Mustafa, “Optimal Turn Prohibition for Deadlock Prevention in Networks with Regular Topologies”, *IEEE Trans on Control of Networks,* accepted, 2014

### 2013

I. Shumsky, O.Keren, M.Karpovsky, ” Robustness of Security-Oriented Binary Codes Under Non-Uniform Distribution of Codewords”, *Proc. Int. Depend Symp., 2013*

P.Luo, Z.Wang and M.G.Karpovsky, “Secure NAND Flash Memories Resilient to Strong Fault-Injection Attacks Using Algebraic Manipulation Detection Codes”, *Proc. Int. Conference on Security and Management, SAM , 2013*

*Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky, “Reliable and Secure Memories Based on Algebraic Manipulation Detection Codes and Robust Error Correction” , Proc. Int. Depend Symp., 2013
*

Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky, ” Secure Memories Resistant to Both Random Errors and Fault Injection Attacks Using Nonlinear Error Correction Codes”, *Proc. Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, 2013*

### 2012

Z.Wang and M.G.Karpovsky, “New Error Detecting Codes for design of Hardware Resistant to Strong Fault Injection Attacks”, *Proc. Int. Conference on Security and Management, SAM *, 2012

Z.Wang and M.G.Karpovsky, “Reliable and Secure Memories Based on Algebraic Manipulation Correction Codes”, *Proc Int Symp. on On-line Testing,* June 2012

L. Levitin, M.G.Karpovsky and M. Mustafa, “Deadlock Prevention in Networks of Workstations with Wormhole Routing“, Distributed Innovations for Business, Engineering and Science, Edited by A. Loo, accepted, 2012.

M.G Karpovsky, L.B.Levitin, M Mustafa, “Deadlock Prevention in Multiprocessor Systems with Wormhole Routing“, Distributed Innovations for Business, Engineering and Science, Edited by A. Loo, accepted, 2012.

Z.Wang and M.G.Karpovsky, “Reliable and Secure Memories Based on Algebraic Manipulation Codes and Robust Error Correction”, submitted, 2012

Z.Wang and M.G.Karpovsky, “New Error Detecting Codes for design of Hardware Resistant to Strong Fault Injection Attacks”, submitted, 2012

### 2011

K.D.Akdemir, Z. Wang, M. G. Karpovsky, and B. Sunar, “Design of Cryptographic Devices Resilient to Fault Injection Attacks Using Nonlinear Robust Codes“, Fault Analysis in Cryptography, M. Joye Editor, 2011

Z.Wang, M.G.Karpovsky and A.Joshi, “Reliable NAND Memories Based on Nonlinear Multi-Error Correcting Codes“, IEEE Trans on VLSI, Vol PP, Issue 99, 2011

Z. Wang and M.G.Karpovsky, “Algebraic Manipulation Detection Codes and Their Application for Design of Secure Cryptographic Devices“, Proc of Int. Symp. on On-Line Testing, 2011

Z. Wang, A.Joshi and M.G.Karpovsky, “Influence of Metallic Tubes on the Reliability of CNTFET SRAMs: Error Mechanisms and Countermeasures“, Proc. GLSVLSI Conference, 2011

Z.Wang, M.G.Karpovsky and A.Joshi, ” Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes “, IEEE Trans on VLSI, Vol PP, Issue 99 , 2011

M.G. Karpovsky and Z. Wang, “Algebraic Manipulation Detection Codes for Secure Communication and Computation Channels”, submitted, 2011

### 2010

L. B. Levitin, M. G. Karpovsky, M. Mustafa, “Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks”, IEEE Transactions on Parallel and Distributed Systems, Vol. 21, no. 9, pp. 1342-1353, September 2010

L.B. Levitin, T. Toffoli, “Heat-to-work conversion by exploiting quantum correlations”. The 10th Conference on Quantum Structures, QS2010, Boston, MA, June 2010.

L.B. Levitin, T. Toffoli, “Work recoverable from two-particle information”. The 10th International Conference on Quantum Communication, Measurement and Computing, QCMC 2010, Brisbane, Australia, July 2010.

Y. Rykalova, L.B. Levitin, R. Brower, “Critical phenomena in discrete-time interconnection networks.” Physica A, 389, No. 22, 15 Nov. 2010, 5259-5278. Published online June 28, 2010.

Z.Wang, M.G.Karpovsky and A.Joshi, “Reliable NAND Memories Based on Nonlinear Multi-Error Correcting Codes”, submitted to IEEE Trans on VLSI,2010

O. Keren, I. Levin, M. G. Karpovsky, “Duplication Based One-to-many Coding for Trojan HW Detection”, submitted to Int. Symp.on Defect and Fault Tolerance in VLSI Systems, 2010

Z. Wang, M. Karpovsky, “Robust FSMs for Cryptographic Devices Resilient to Strong Fault Injection Attacks” , Proc Int Symp. on On-line Tesing, July 2010

Z. Wang, M. G. Karpovsky and A. Joshi, ” Reliable MLC NAND Flash Memories Based on Non-Linear t-error Correcting Codes” Proc. Int. Conf. on Dependable Systems and Networks, June 2010

Z. Wang, M. G. Karpovsky, K. Kulikowski, “Design of Memories with Concurrent Error Detection and Correction by Non-Linear SEC-DED Codes”, Journal of Electronic Testing, vol. 26, Oct 2010

### 2009

Y. Rykalova, L. B. Levitin, and R. Brower, “Multiprocessor networks with small buffers”. Proc. of the 12th Communications and Networking Simulation Symposium, CNS 09, March 22 – 27, 2009, San Diego, CA., USA

L.B. Levitin, T.Toffoli, “A unified bound on the rate of quantum dynamics”. In ¡°Quantum Communication, Measurement and Computing¡±, A. Lvovsky, ed., American Institute of Physics, Melville, NY, 2009, 13-16.

L. B. Levitin, M. Karpovsky, M. Mustafa,”Deadlock prevention by turn prohibition in interconnection networks”, Proc. of the IEEE Intern. Parallel and Distributed Processing Symposium, IPDPS 2009, May 25- 29, 2009

L. B. Levitin, T. Toffoli, “Fundamental limit on the rate of quantum dynamics: the unified bound is tight.” Phys. Rev. Letters, 103, 16 Oct. 2009, 160502.

Z. Wang, M.G. Karpovsky, B.Sunar, A.Joshi, “Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes”, Proc. Int. Conf. on Information, Communications Security, Dec. 2009

S. Baranov, I. Levin, O.Keren, M. G. Karpovsky, “Designing Fault Tolerant FSMs by Nano-PLAs”, Proc. Int. On-Line Testing Symp, June 2009

Z. Wang, M. G. Karpovsky, B Sunar, “Multilinear Codes for Robust Error Detection”, Proc. Int. On-Line Testing Symp., June, 2009

Z. Wang, M. G. Karpovsky, K. Kulikowski, “Replacing Linear Hamming Codes by Robust Nonlinear Codes Results in Reliability Improvement for Memories”c, Proc. Int. Symp. Dependable Computing, July 2009

R. S. Stankovic, M. G. Karpovsky, and C. Moraga, ” Remarks on Codes, Spectral Transforms, and Decision Diagrams” , in Tabush, I., Egiazarian, K., Gabouj, M., (eds.), pp 226-246, July, 2009

L. Levitin, M. G. Karpovsky, M. Mustafa, “Deadlock prevention by Turn Prohibitions in Interconnection Networks” , Proc. of Int. Workshop on Communication Architecture for Clusters, CAC, Rome, May, 2009

K. Kulikowski, M. G. Karpovsky, “Robust Correction of Repeating Errors in Combinational Circuits by Nonlinear Codes”, submitted to IET, Dec 2009

L.B. Levitin, M. G. Karpovsky, M. Mustafa, “Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks” , IEEE Trans. Parallel and Distributed Systems., vol. 21, No. 9, Sept 2010 , pp. 1342-1353 (published on-line Dec, 2009)

### 2008

L.B. Levitin, T. Toffoli,”Orthogonalization time revisited.” The 9th Conference on Quantum Structures, QS2008, July 2008, Sopot, Poland.

L.B. Levitin, T. Toffoli, “A generalized bound on the rate of quantum dynamics”. The 9th International Conference on Quantum Communication, Measurement and Computing, QCMC 2008, Calgary, Canada, August 2008.

Z. El-Jamous, L.B. Levitin, M Mustafa, “Comparison of turn prohibition algorithms for deadlock prevention in interconnection networks”. IASTED Conference on Communication Systems and Networks, September 2008, Palma de Mallorca, Spain.

Z. El-Jamous, L.B. Levitin, M Mustafa, M. Karpovsky, “Performance of Cycle-Breaking Algorithms for Deadlock and Livelock Prevention in Communication Networks”. OPNETWORK 2008, Washington, D.C., August 2008.

Y. Rykalova, L. B. Levitin, and R. Brower, “Interconnection networks with heterogeneous activity or finite buffers: beyond Jackson¡¯s theorem”. Proc. of the 11th Communications and Networking Simulation Symposium, CNS 08, Ottawa, Canada, April 14 – April 17, 2008

O.Keren, I, Levin, M. G. Karpovsky, “Non-redundant Scheme for Arbitrary Error Detection in Combinational Circuits”, Proceedings of 16th IFIP/IEEE Conference on Very Large Scale Integration, 2008

K. Kulikowski, Z. Wang, M.G. Karpovsky, “Comparative Analysis of Fault Attack Resistant Architectures for Private and Public Key Cryptosystems”, Proc of Int. Workshop on Fault-tolerant Cryptographic Devices, 2008

K. Kulikowski, M. G. Karpovsky, A. Taubin, Z. Wang, “System-Level Concurrent Fault Detection for Secure QDI Asynchronous Circuits”, Proceedings of Workshop on Dependable and Secure Nanocomputing, DSN-08, 2008

K. Kulikowski, V. Venkataraman, Z. Wang, A. Taubin, M.G. Karpovsky, “Asynchronous Balanced Gates Tolerant to Interconnect Variability”, Proceedings of ISCAS, 2008

M.G.Karpovsky, K. Kulikowski, Z, Wang, “On-Line Self Error Detection with Equal Protection Against All Errors”, Int. Journal of Highly Reliable Electronic System Design, June 2008

### 2007

L. B. Levitin, M. G. Karpovsky, M. Mustafa and L. Zakrevski, “New Algorithm for Finding Cycle-Breaking Sets of Turns in a Graph”, volume 10, no. 2, Journal of Graph Algorithms and Applications, 2007.

Y. Rykalova, L. B. Levitin, and R. Brower, “Performance model of a multiprocessor interconnection network”. Theory and simulation, Proc. of the 10th Communications and Networking Simulation Symposium, CNS 07, Norfolk, VA, March 2007, 100-105

Y. Rykalova, L. B. Levitin, and R. Brower, “Analysis and simulation of a model of multiprocessor networks”, Proc. of Advances in Computer Science and Technology, ACST 2007, Phuket, Tailand, April 2007, 200-205.

Y. Rykalova, L.B. Levitin, and R. Brower, “Modeling of latency and saturation phenomena in interconnection networks”, Proc. of the IEEE Symposium on Computers and Communications, ISCC¡¯07, Aveiro, Portugal, July 2007

L.B. Levitin, T. Toffoli, “Thermodynamic cost of reversible computing”. Phys. Rev. Letters, 99, no.11, Sept. 2007, 110502.

K. J. Kulikowski, M. G. Karpovsky, A.Taubin, “Robust Codes and Robust, Fault Tolerant Architectures of the Advanced Encryption Standard”, Journal of System Architecture, vol. 53, pp138-149, 2007

M.G.Karpovsky, K. Kulikowski, Z, Wang, “Robust Error Detection in Communication and Computation Channels”, Keynote paper, Int. Workshop on Spectral Techniques, 2007

### 2006

Konrad J. Kulikowski, Alexander Smirnov, Alexander Taubin. “Automated Dsign of Cryptographic Devices Resistant to Multiple Side-Channel Attacks”. Workshop on Cryptographic Hardware and Embedded Systems 2006 (CHES’06) Yokohama, Japan. October 2006

I.Honkala, M.G.Karpovsky, L.B.Levitin, “On Robust and Dynamic Identifying Codes” , IEEE Trans Info Theory, Feb 2006, pp599-613

Smirnov A., Taubin A., and Karpovsky M., “On Automatic Synthesis of Data Dependent Micropipelines” Proc. Int. Workshop on Logic and Synthesis, 2006

I. Levin, T. Keren, G. Kolotov, M.G. Karpovsky, “PIECEWISE LINERIZATION OF LOGIC FUNCTIONS” , Proc Int Workshop on Spectral Techniques, 2006

R. Stankovic, Jaakko Astola, Mark Karpovsky, “SOME HISTORIC REMARKS ON THE SAMPLING THEOREM”, Proc Int Workshop on Spectral Techniques, 2006

G.Gaubatz, B.Sunar, M.G.Karpovsky, “Robust Residue Codes for Fault-Tolerant Public-Key Arithmetic”, Proc of Int. Workshop on Fault Detection and Tolerance in Cryptography, 2006

Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin. “DPA on Faulty Cryptographic Hardware and Countermeasures”. Workshop on Fault Diagnosis and Tolerance in Cryptography 2006 (FTDC’06) Yokohama, Japan. October 2006.

Konrad J. Kulikowski K, Mark Karpovsky, Alexander Taubin. “Power Attacks onSecure Hardware Based on Early Propagation of Data”. International On-LineTesting Symposium (IOLTS’06) Lake of Como, Italy, July 2006.

F.De Pelegrini, D.Starobinski, M.G.Karpovsky, L.B.Levitin, “Scalable CycleBreaking Algorithms For Gigabit Ethernet Backbones”, Journal of OpticalNetworking, Vol.5, N.1 Jan. 2006, pp.1-23

### 2005

Levin I., Stankovic R., Karpovsky M., Astola J., (2005) “Construction of PlanarBDDs by Using Linearization and Decomposition”, Proc. of FourteenthInternational Workshop on Logic and Synthesis, Lake Arrowhead, California, pp.132-139.

A.Smirnov, A.Taubin, M.Su, and M.G.Karpovsky, “An Automated Fine-Grain PipeliningUsing Domino Style Asynchronous Library”, Proc. ACSD 2005 : Fifth InternationalConference on Application of Concurrency to System Design

Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin , “Robust Codes forFault Attack Resistant Cryptographic Hardware”, Workshop on Fault Diagnosis andTolerance in Cryptography 2005 (FTDC05), September 2005.

Konrad J. Kulikowski, Mark Karpovsky, Alexander Taubin, ” Memories with RobustSelf Error Detection Invariant to Error Distributions”, In Informal Proceedingsof the 10th European Test Symposium (ETS05), May 2005.

Konrad J. Kulikowski, Ming Su, Alexander Smirnov, Alexander Taubin, MarkKarpovsky, and Daniel MacDonald, “Delay Insensitive Encoding and PowerAnalysis: A Balancing Act”, Proc. 11th Int. Symp. on Asynchronous Circuits andSystems, 2005

R.Stanckovic, and M.G.Karpovsky, “Remarks on Calculation of Autocorrelation onFinite Dyadic Groups by Local Transformations of Decision Diagrams”, LectureNotes Springer and Verlag, 2005

R.S.Stankovic, J.T.Aastola and M.G.Karpovsky, “Remarks on History of AbstractHarmonic Analysis”, Proc. Fifth Int. Workshop on Spectral Methods and SignalProcessing, 2005

### 2004

M. Karpovsky and A. Taubin. “New Class of Nonlinear Systematic Error DetectingCodes”. IEEE Transactions on Information Theory. IEEE Trans Info Theory, Vol 50,No.8, 2004, pp.1818-1820 .

M. Karpovsky, K. Kulikowski and A. Taubin. “Differential Fault Analysis AttackResistant Architectures for the Advanced Encryption Standard. CARDIS 04:Sixth smart Card Research and Advanced Application IFIP Conference, August,2004.

Karpovsky, M.G., Stankovic, R.S., Moraga, C., ”Spectral techniques in binary andmultiple-valued switching theory, a review of results in the decade 1991-2000?Multiple-Valued Logic and Soft Computing, Vol. 10, N. 3, 2004, 261-286

M. Karpovsky, K. Kulikowski and A. Taubin. Robust Protection againstFault-Injection Attacks of Smart Cards Implementing the Advanced EncryptionStandard. DSN04: The International Conference on Dependable Systems andNetworks, June, 2004

Smirnov A., Taubin A., Karpovsky M. and Rozenblyum L. Gate Transfer LevelSynthesis as an Automated Approach to Fine-Grain Pipelining in Workshop onToken Based Computing (ToBaCo). June 22, 2004. Bologna, Italy.

Smirnov A., Taubin A., and Karpovsky M. Automated Pipelining in ASIC SynthesisMethodology: Gate Transfer Level. in IWLS 2004 Thirteenth InternationalWorkshop on Logic and Synthesis. June 2-4, 2004. Temecula, California, USA.

Francesco de Pellegrini, David Starobinski, Mark Karpovsky and Lev Levitin,“Scalable Cycle-Breaking Algorithms for Gigabit Ethernet Backbones,” IEEEINFOCOM 2004, Hong Kong, March 2004

M.G.Karpovsky, R.Stancovic and J.Aastola, “Construction of Linearly TransformedPlanar BDDs by Walsh Coefficients”, Proc. ISCAS, 2004

Kolotov Y., Levin, I., Ostrovsky V., Karpovsky M.G, “Software Tool for BDDOptimizing by Using Autocorrelation Functions”. Proc. of the 23-th IEEEConvention of EEEI, 2004, pp129-132.

I.Levin, M.G.Karpovsky, S.Ostanin, V.Sinelnikov, “Designing Circuits DetectingDifferent Types of Faults”, *WSEN Transactions on Electronics, Issue 2, Vol. 1,Apr 2004, pp.396-404*

Stankovic, R.S., Karpovsky, M.G., and J.T. Aastola, “Reduction of the Number ofCoefficients in Arithmetic Expressions by Autocorrelation Functions”, Proc.2004 International Workshop on Spectral Methods and Multirate SignalProcessing, SMMSP2004

### 2003

A. Smirnov and A.Taubin, Weaver ?a synthesis flow (beta version) for fine grainpipelining based on a commercial synchronous engine. IEEE InternationalSymposium on Advanced Research in Asynchronous Circuits and Systems, CADTutorial Program. May 2003.

D. Starobinski, A. Trachtenberg, and S. Agarwal, “Efficient PDAsynchronization”, IEEE Trans. on Mobile Computing 2:1, January-March 2003

Rajesh Krishnan and David Starobinski, “Message-Efficient Self-Organization ofWireless Sensor Networks,” to appear in IEEE WCNC 2003.

David Starobinski, Mark Karpovsky, and Lev Zakrevski, “Application of Network Calculus to General Topologies using Turn-Prohibition,” to appear in IEEE/ACM Transactions on Networking.

Saikat Ray, Jeffrey Carruthers, and David Starobinski, “RTS/CTS-inducedCongestion in Ad-Hoc Wireless LANs,” IEEE WCNC 2003.

Ray S., Ugrangsi R., De Pellegrini F., Trachtenberg A., Starobinski D., “RobustLocation Detection for Emergency Sensor Networks”, proceedings of IEEE INFOCOM2003, San Francisco, CA.

### 2002

M.G. Karpovsky, M.Mustafa, R.Mathur,”Fault-Tolerant Unicast Wormhole Routing inIrregular Computer Networks”,Proc. of the Conference on Parallel andDistributed Computing and Systems, PDSC 2002.

L.B. Levitin, M.G. Karpovsky, “Deadlock Prevention in Networks Modeled asWeighted Graphs”, Proc. ICINSAT-2002 Conf, 2002.

R. Stancovic, M.G. Karpovsky, “Remarks on the Number of Logical Networks withthe same Complexity Derived from Spectral Decision Diagrams”. Proc. Int. TICSWorkshop on Spectral Methods and Multirate Signal Processing, SMMSP’02,Toulouse, France, September 7-8, 2002, pp163-170.

I. Levin, V. Ostrovsky, S. Ostanin, M.G. Karpovsky, “Self-Checking SequentialCircuits with Self-Healing”, Proc of VLSI Symposium GLSVLSI-2002, 2002.

M.G.Karpovsky, R.Stancovic, J. Aastola, “Reduction of Sizes of Decision Diagramsby Autocorrelation Fuctions”, IEEE Trans on Computers, 2002.

I. Levin, M. G. Karpovsky, S. Ostanin, “Sequential Circuits applicable forDetection of Faults”, Proc. of 8th Int.Workshop on On-Line Testing, 2002.

I.Honkala, M.G.Karpovsky, S.Litsyn “Cycles Identifying Vertices and Edges inBinary Hypercubes and Two-Dimensional Tori”, Discrete Applied Mathematics,2002.

D.Starobinski, M.G.Karpovsky, L.Zakrevsky “Applications of Network Calculus toGeneral Topologies” IEEE/ACM Transactions on Networking, 2002.

M. Karpovsky, R. Stankovic, C.Moraga, “Spectral Techniques in Binary andMultiple-Valued Switching Theory”, International Journal on Multiple-ValuedLogic, 2002.

D. Starobinski, M.G.Karpovsky, L. Zakrevski, “Application of Network Calculus toGeneral Topologies Using Turn Prohibitions”, Proc. INFOCOM 2002.

A. Trachtenberg, Designing Lexicographic Codes with a Given Trellis Complexity,IEEE Trans. Inf. Theory, January 2002.

T. Etzion, A. Trachtenberg, and A. Vardy, Which Codes have Cycle-Free TannerGraphs? IEEE Trans. Inf. Theory, 45:6.

J. Cortadella, M. Kishinevsky, S.M. Burns, A. Kondratyev, L. Lavagno, K.S.Stevens, A. Taubin and A. Yakovlev, Lazy transition systems and asynchronouscircuit synthesis with relative timing assumptions. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, Feb.2002, pp. 109-130.

A. Taubin and M. Karpovsky Devices Resistant to Attacks. Design Methodology.2002 Fall IEEE Conference on Technologies for Homeland Security, November13-14, 2002

A.Taubin, K. Fant and J. McCardle. Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing, Proceedings, 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors.ICCD?002, p.p.104-111

A. Kondratyev, L. Neukom, O. Roig, A. Taubin and K. Fant CheckingDelay-Insensitivity: 104 Gates and Beyond. In International Symposium onAdvanced Research in Asynchronous Circuits and Systems, April 2002, p. 149-157

S. Agarwal, D. Starboinski, and A. Trachtenberg, “On the scalability of datasynchronization protocols for PDAs and mobile devices”,IEEE Network:Scalability in Comm.Networks, July, 2002.

A. Trachtenberg, “Designing Lexicographic Codes with a Given TrellisComplexity”, IEEE Trans. Inf. Theory, January 2002:

### 2001

Y. Minsky, A. Trachtenberg, and R. Zippel, Set Reconciliation with NearlyOptimal Communication Complexity, submitted. 2001

M.G.Karpovsky, R.Stankovic, C.Moraga, “Recent Results in Applications ofSpectral Techniques in Binary and Multiple-Valued Switching Theory”, Proc ofInt. Conf on Computer Intelligence and Information Technologies, 2001.

I.Honkala, M.G.Karpovsky, S.Litsyn, “On Identification of Vertices and EdgesUsing Cycles”, Proc. AAECC-14, 2001, pp308-314.

M. Karpovsky, L. Levitin, A. Trachtenberg, “Data Verification and Reconciliationwith Generalized Error Control Codes”, Proc. of 39th Annual Allerton Conferenceon Communication, Control, and Computing, 2001.

A. Trachtenberg, M. Karpovsky, “Space-Time Turn Prohibitions for Low DensityParity-Check Codes”, Proc. of 39th Annual Allerton Conference on Communication,Control, and Computing, 2001.

M. Karpovsky, L. Zakrevski, M. Mustafa, A. Agarwal, “The Generalized TurnProhibition Model for Multicast Routing in Irregular Networks,” Proc. ofThirteenth IASTED International Conference on Parallel and DistributedComputing and Systems (PDCS 2001).

M. Karpovsky, R. Stankovic, J. Astola, “Construction of Linearly TransformedBinary Decision Diagrams by Autocorrelation Functions”, Proceedings ofInternational TICSP Workshop on Spectral Methods and Multirate SignalProcessing, SMMSP’2001, Pula, Croatia, 2001.

I. Levin, V. Sinelnikov, M. Karpovsky, “Synthesis of ASM-based Self-CheckingControllers”, Proceedings of International Conference on Digital SystemsDesign, DSD’2001.

P.K.Lala, M.G.Karpovsky, “An Approach for Designing On-line Testable StateMachines”, Proc. International Workshop on On-line Testing, 2001.

U.Blass, I.Honkala, M.G.Karpovsky, S. Litsyn, “Short Dominating Paths and Cyclesin Hypercubes”, Annals of Combinatorics 5, 2001.

David Starobinski and David Tse, “Probabilistic Methods for Web Caching” ,Performance Evaluation , Vol 46, Nos. 2-3, pp. 125-137, October 2001.

### 2000

I. Levin, M. Karpovsky, V. Sinelnikov, “Architecture of FPGA-based ConcurrentChecking FSM”, Proceedings of the Third International Electronic Circuits andSystems Conference, Bratislava, Slovakia, September 5-7, 2000.

M.G.Karpovsky, R.S.Stankovic, J.T.Astola, “Spectral Techniques for Design andTesting of Computer Hardware”, Keynote Paper, Proc. First Int. Workshop onSpectral Techniques and Logical Design for Future Digital Systems, Tampere,Finland, June, 2000.

David Starobinski and Moshe Sidi, “Modeling and Analysis of Power-TailDistributions via Classical Teletraffic Methods” ,Queueing Systems (QUESTA),Vol. 36, Nos. 1-3, pp. 243-267, November 2000.

S. Jaiswal, L. Zakrevski, M.G. Karpovsky, “Wormhole Message Routing in Networksof Workstations”, PDCS-2000.

Michiel Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex KondratyevAsynchronous Design Using Commercial HDL Synthesis Tools. In InternationalSymposium on Advanced Research in Asynchronous Circuits and Systems, April2000.

### 1999

M.G. Karpovsky, K. Chakrabarty, L.B. Levitin, D. Avresky, “On the Covering ofVertices for Fault-Diagnosis in Hypercubes”, Information Processing Letters,69, 1999, pp.99-103.

L. Zakrevski, M.G. Karpovsky, “Fault-Tolerant Routing in Computer Networks”,Proc. Int. Conf. On Parallel and Distributed Processing Techniques andApplications, vol. 4, 1999, pp.2279-2287.

L. Zakrevski, S. Jaiswal, L.B. Levitin, M.G. Karpovsky, “A New Method forDeadlock Elimination in Computer Networks with Irregular Topologies”, Proc.Int. Conf. On Parallel and Distributed Computer Systems, 1999.

L. Zakrevski, S. Jaiswal, M.G. Karpovsky, “Unicast Message Routing inCommunication Networks with Irregular Topologies”, Proc. of CAD-99, 1999.

A. Taubin, A. Kondratyev, J. Cortadella, and L. Lavagno. Behavioraltransformations to increase the noise immunity of asynchronous specifications.In International Symposium on Advanced Research in Asynchronous Circuits andSystems, pages 36-47, April 1999.

A. Taubin, A. Kondratyev, J. Cortadella, and L. Lavagno. Crosstalk noiseavoidance in asynchronous circuits. In Proceedings of the A CM/IEEEInternational Workshop on Timing Issues in the Specification and Synthesis ofDigital Systems (TA U), pages 123-128, March 1999.

### 1998

V. Iyenger and K. Chakrabarty. An efficient finite-state machine implementationof Huffman decoders. Inf. Processing Lett. , pp. 271-275, 1998.

M. G. Karpovsky, K. Chakrabarty and L. B. Levitin. A new class of codes foridentification of vertices ?IEEE Trans. On Inf. Theory, March 1998.

Lev. B. Levitin. Energy requirements in quantum communication. Int. J. ofTheoretical Physics, 1998.

Lev. B. Levitin. Energy cost of information transmission (along the path ofunderstanding). Physica D., 1998.

N. Margolus and Lev B. Levitin. The maximum speed of dynamic evolution. PhysicaD., 1998 .

M. G. Karpovsky. Integrated on-line and off-line error detection mechanism. VLSIJ., 1998.

Iyengar, K. Chakrabarty and B. T. Murray. Built-in self-testing of sequentialcircuits ?VLSI Test Symp., 1998.

M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha, and A. Taubin. Partialscan delay fault testing of asynchronous circuits. IEEE Transactions onComputer-Aided Design, 17(11):1184-1199, 1998.

A. Kondratyev, M. Kishinevsky, A. Taubin, J. Cortadella, and L. Lavagno. The useof Petri nets for the design and verification of asynchronous circuits andsystems. Journal of Circuits, Systems, and Computers, 8(1):67-118, 1998.

A. Taubin, M. Kishinevsky, and A. Kondratyev. Deadlock prevention using Petrinets and their unfoldings. International Journal of Advanced ManufacturingTechnology, 14(10):750-759,1998.

A. Kondratyev, M. Kishinevsky, A. Taubin, and S. Ten. Analysis of Petri nets byordering relations in reduced unfoldings. Formal Methods in System Design,12(1):5-38, 1998.

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Taubin, and A.Yakovlev. Lazy transition systems: application to timing optimization ofasynchronous circuits. In Proceedings of the International Conference onComputer-Aided Design, pages 324-331, November 1998.

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A.Taubin, and A.Yakovlev. Identifying state coding conflicts in asynchronous systemspecifications using Petri net unfoldings. In Proc. of the InternationalConference on Application of Concurrency to System Design (CSD ’98), pages152-163, Fukushima, Japan, March 1998.

### 1997

D. Avresky, V. Shurbanov and R. Horst. The effect of router arbitration policyMicroprocessors and Microsystems, Elsevier Science, 1997.

D. Avresky. Reconfiguration of faulty hypercubes. Int. J. of Computer Systems Sc. and Engineering, CRL Publishing Ltd., United Kingdom, 1997.

D. Avresky, S. Geoghegan and P. K. Tapadiya. A software-based fault injectiontool ?SOFIT. Int. J. of Computer Systems Sc. and Engineering, CRL PublishingLtd., United Kingdom, 1997.

D. Avresky and C. Cunningham. Single source fault-tolerant broadcastingMicroprocessors and Microsystems, Elsevier Science, 1997.

D. Avresky. Formal verification of behavioral and timing properties protocols.Computer Communications J., 1997.

K. Chakrabarty and J. P. Hayes. Zero-aliasing space compaction. IEEE Trans. OnVLSI Systems, 1997.

K. Chakrabarty and J. P. Hayes. On the quality of accumulator-based compactionof test responses. IEEE Trans. on CAD, 1997.

D. Das and M. G. Karpovsky. Exhaustive and near exhaustive memory testing. J. ofElectronic Testing: Theory and Applications, pp. 215-229, 1997.

V. N. Yarmolik, A.I. Yanushkevich and M. G. Karpovsky. IDDQ testing of systolicCMOS networks. Micro-electronics Bulletin Russian Acad. of Sc., pp. 25-29,1997.

A.Zakrevskij and L. Zakrevski. Synthesis of the shortest Reed-Mullerrealization. Doklady of the Acad. of Sc. Of Belarus, pp. 5-9, 1997.

A.Zakrevskij and L. Zakrevski. Diagnosis of stuck-at faults in EXOR- circuits.Automatic and Computer Technik, pp. 23-31, 1997.

Moshe Sidi and David Starobinski, “New Call Blocking versus Handoff Blocking inCellular Networks”, ACM Journal of Wireless Networks, Vol. 3, No. 1, pp. 15-27,March 1997.

V. Shurbanov, D. Avresky, R. Horst and (et al). A scalability study of ServerNettopologies. Int. Conf. On Parallel and Distributed systems, 1997.

D. Avresky and S. Vassilaras. Automated formal verification ?Int. Conf. OnComputers and Communications, 1997.

C. Cunningham and D. Avresky. Dynamic fault recovery ?Int. Workshop onFault-Tolerant, Parallel and Distributed Systems, 1997.

K. Chakrabarty, B. T. Murray, J. Liu and M. Zhu. Test width compression. Int.Test Conf., pp. 328-337, 1997.

V. Iyengar, K. Chakrabarty and B. T. Murray. Test set encoding for efficientsequential circuit testing. Instr. And Meas. Tech. Conf., pp. 1442-1447, 1997.

V. Iyengar, K. Chakrabarty and B. T. Murray. Built-in self-testing with completefault coverage ?IEEE North Atlantic Test Workshop, pp. 15-18, 1997.

L. Levitin. Remarks on conditional density matrix, entropy and information. Int.Workshop on Quantum Computation, 1997.

L. Levitin. Minimum energy in information transmission. Int. Conf. On CAD ofDiscrete Devices, pp. 98-102, 1997.

A.Zakrevskij and L. Zakrevski. Efficient algorithms for minimization ofpolynomial representation ?Int. Workshop on VLSI Systems, pp. 49-50, 1997.

A. Zakrevskij and L. Zakrevski. Fast algorithm for minimizing Reed-Mullerexpansions ?Int. Symposium on Multiple-Valued Logic, pp. 61-65, 1997.

A. Taubin, A. Kondratyev, and M. Kishinevsky. Applications of Petri netsunfoldings to asynchronous design. In 1997 IEEE International Conference onSystems, Man, and Cybernetics, volume 5, pages 4279-4284, Orlando, Florida,October 1997.

M. Kishinevsky, J. Cortadella, A. Kondratyev, L. Lavagno, A. Taubin, and A.Yakovlev. Coupling asynchrony and interrupts: Place chart nets and theirsynthesis. In International Conference on Application and Theory of Petri Nets,Proc. 18th Int. Conference, volume 1248 of Lecture Notes in Computer Science,pages 328-347, Toulouse, France, June 1997. Springer Verlag.

Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Saldanha, andAlexander Taubin. Partial scan delay fault testing of asynchronous circuits. InProceedings of the International Conference on Computer-Aided Design, pages728-735, November 1997.

Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Saldanha, andAlexander Taubin. Delay fault testing of asynchronous sequential circuits. InProc. of IWLS ’97: International Workshop on Logic Synthesis, May 1997.

### 1996

D. Avresky and J. Arlat. Functional programming for fault-tolerance. ISCAJ. of Computers and their Applications, 1996.

D. Avresky, J. Arlat, J. C. Laprie and Y. Crouzet. Fault injection for theformal testing of fault-tolerance. IEEE Trans. on Reliability, September 1996.

K. Chakrabarty and J. P. Hayes. Test response compaction using multiplexedparity trees. IEEE Trans. on CAD, pp. 1399-1408, 1996.

K. Chakrabarty and J. P. Hayes. Balance testing and balance-testable design. J.of electronic Testing: Theory and Applications, pp. 71-86, 1996.

M.G. Karpovsky and V. N. Yarmolik. Transparent random access memory testing.JETTA, pp. 251-266, 1996.

Lev B. Levitin. On the quantum measure of information. Annales de la FondationLouis de Broglie, pp. 345-348, 1996.

Lev B. Levitin, R. Gunther, B. Shapiro and P. Wagner. Zipf’s law and the effectof ranking ?Int. J. of Theoretical Physics, pp. 395-417, 1996.

A Zakrevsky and L. Zakrevski. Test generation and diagnosis for EXOR- circuits.Doklady of the Academy of Sc. of Belarus, pp. 7-11, 1996.

L. Zakrevski. Superfast algorithm for canonical Reed-Muller form minimizationfor weakly defined systems of Boolean functions. Logic Design, pp. 76-85, 1996.

L. Zakrevski and V. N. Yarmolik. Synthesis of optimal signature analyzer forerror detection in logic devices. Technical Cybernetics, pp. 126-130, 1996.

D. Avresky et al. Formal verification of protocols. Int. Workshop on EmbeddedFault-Tolerant Systems, 1996.

S.J. Geoghegan and D. Avresky. Method for designing and placing check sets. Int.Symp. On Software reliability Engineering, 1996.

R. Wilkinson and D. Avresky. Implementation of a scalable reconfigurationalgorithm. Int. Conf. On Massively Parallel Computing Systems, 1996.

S.J. Geoghegan ad D. Avresky. Design, verification and validation of self-checking software components. Int. Conf. On computers and Communications, 1996.

S. Gerber ad D. Avresky. Evaluation of software diversity for detecting hardwarefaults. Int. On-line Test Workshop, 1996.

K. Chakrabarty, M. G. Karpovsky and L. Levitin. Fault-tolerant multiprocessorsystems. Workshop on Fault-Tolerant and Distributed Systems, 1996.

M. G. Karpovsky, D. Das and H. Vardhan. BIST for detection of coupling-faults.Int. Workshop on Memory Tech., Design and Test, 1996.

L. Levitin. Energy cost of information transmission. Int. Workshop on Physicsand computation, 1996.

L. Levitin. Energy requirements in quantum communication. Quantum Structures,1996.

N. Margolus and L. Levitin. Quantum computational dynamics. Int. Workshop onQuantum Computation, 1996.

L. Zakrevki. Detection of stuck-at faults in AND/EXOR combinational circuits.Int. Conf. On Mathematics and Informatics, Kishinev, pp. 123, 1996.

A. Kondratyev, M. Kishinevsky, A. Taubin, and S. Ten. A structural approach forthe analysis of Petri nets by reduced unfoldings. In International Conferenceon Application and Theory of Petri Nets, Proc. 17th Int. Conference, volume1091 of Lecture Notes in Computer Science, pages 346-365, Osaka, Japan, June1996. Springer-Verlag.

A. Taubin, A. Kondratyev, M. Kishinevsky, and S. Ten. Deadlock prevention usingPetri net unfoldings. In Computational Engineering in Systems Applications.CESA ’96 IMACS/IEEE/SMC Multiconference, pages 426-431, July 1996.

A. Taubin, A. Kondratyev, and M. Kishinevsky. Deadlock prevention by Petri netstransformations. In Proc. of IEICE Concurrent Systems Technology Conference,CST-96, Aizu-Wakamatsu, Japan, May 1996.

### 1995

K. Chakrabarty and J. P. Hayes. Cumulative balance testing ?IEEE Trans. on VLSISystems, pp. 72-83, 1995.

M. G. Karpovsky. Applications of spectral techniques for off-line testing.Berichte zur Angewandten Informatik, 1995.

M. G. Karpovsky, T. D. Roziner and C. Moraga. Fault detection in multiprocessorsystems ?IEEE Trans. on Computers, pp. 383-393, 1995.

K. Chakrabarty, B. T. Murray and J. P. Hayes. Optimal space compaction of testresponses. Int. test Conf., pp. 834-843, 1995.

V. N. Yarmolik, Y. V. Bykov and M. G. Karpovsky. Test sets for internal accesstesting. Int. Conf. On CAD, pp. 131-141, 1995.

M. G. Karpovsky and V. N. Yarmolik. Testability measures and testcomplexities. Int. Workshop on IDDQ Testing, pp. 9-14, 1995.

L. Levitin. Single-error-correcting codes for magnetic recording. Int. Symp. OnInf. Theory, 1995.

L. Levitin and F. S. Vainstein. Bit-shift error correction in (d,k) codes.AAECC, 1995.

L. Zakrevski. Control flow error detection with signature analyzers. Int. Conf.On CAD of Discrete Devices, pp. 165-168, 1995.

L. Zakrevski. Combining concurrent error detection with off-line test. On-lineTesting Workshop, pp. 201-205, 1995.

L. Kazarjan and Zakrevski L. Using random test generation for the diagnostics.Int. Mixed Signal Testing Workshop, pp. 92-94, 1995.

L. Zakrevski. Calculation of multiple sets of weights for scan- based random testing. Int. Conf. “Gronics-95? pp. 43-46, 1995.

S. Ten, A. Kondratyev, M. Kishinevsky, and A. Taubin. Software tool offering Petri net unfolding construction. In Proceedings of the 16th International Conference on Application and Theory of Petri Nets. Tool presentation, Torino, Italy, June 1995

## Books and Book Chapters

K. Chakrabarty, M. Karpovsky and L. Levitin. Fault isolation and diagnosis inmultiprocessor systems with point-to-point communication links. Fault- TolerantParallel and Distributed Systems, Kluwer Academic Press, 1998.

D. Avresky and D. Kaeli, eds. Fault-Tolerant Parallel and Distributed Systems,Kluwer Academic Press, 1997. D. Avresky and D. Kaeli. On-line fault recoveryfor wormhole routed two- dimensional meshes. Fault-Tolerant Parallel andDistributed Systems, Kluwer Academic Press, 1997.

D. Avresky and D. K. Pradhan. Fault-Tolerant Parallel and Distributed Systems,Computer Society Press, 1995. L. Levitin. Optimal quantum measurements for pureand mixed states. Quantum Communication and Measurements, 1995.