Toward a Faster, Better, Smaller Chip

New Research Aims to Reduce Defects in Shrinking Integrated Circuit Elements

By Mark Dwortzan

Professor Bennett Goldberg (Physics, ECE)
Professor Bennett Goldberg (Physics, ECE)

Professor Selim Ünlü (ECE)
Professor Selim Ünlü (ECE)

Is there a limit to how much data you can fit in your iPod? The answer may lie at the nanoscale. Over the past decade, as PCs and other consumer electronic devices have packed more and more information into faster, higher-density chips, the feature size used in semiconductor integrated circuit (IC) fabrication has shrunk from 180 to 45 nanometers—and the industry now has its sights on reducing that figure to 11 nanometers. These tiny feature sizes are making ICs impossible to inspect and analyze with conventional optical imaging methods, challenging researchers and worrying manufacturers who aim to deliver chips free of processing faults and circuit defects. 

To tackle this problem, the Intelligence Advanced Research Projects Activity (IARPA) recently awarded two grants totaling $5.3 million to an interdisciplinary research team from Boston University—Professor Bennett Goldberg (Physics, ECE), Professor Selim Ünlü (ECE), Associate Professor Jerome Mertz (BME) and Professor Thomas Bifano (ME)—along with an industrial partner, DCG Systems, Inc. of California—the leading IC diagnostics company. The team plans to spend the next four years applying novel imaging approaches to pinpoint and resolve defects on next generation ICs.

Imaging Smaller and Smaller Features
The effort will build on a state-of-the-art subsurface microscopy technique developed since 2000 by Ünlü, Goldberg and their students which uses a spherical microlens to boost the optical resolution of images taken of the transistors at the heart of integrated circuits. With laboratory data demonstrating imaging of a 45-nanometer circuit node, the researchers are now working on further improvements to accommodate the semiconductor industry’s quest for smaller and smaller feature sizes.

Their goal is to enable IC imaging and fault isolation in 22-nanometer (nm) technologies and in 11-nm technologies, improve imaging resolution by a factor of more than three (from 250 nm to 80 nm) and apply the technology to a state-of-the-art failure analysis lab tool developed by DCG Systems.

“Each step in the development of new IC chips requires new analysis tools, and potential delays due to unexpected faults can be very costly, with minutes measured in thousands of dollars,” said Ünlü. “Progress in this area will lead not only to more cost-effective chip development, but also to better, faster and more efficient automotive, medical and other potentially lifesaving devices that depend on reliable integrated circuits.”

Incorporating Novel Photonic Technologies
To inspect and analyze an integrated circuit, engineers focus laser light to a point comparable to the smallest feature size and measure the reflected signal or monitor the electrical response. In some cases they also collect time bursts of light from the transistor as it switches from “on” to “off.” Since top inspection is prevented by the dense metallic multilayer structure, backside imaging through the silicon substrate is necessary. Ünlü and Goldberg’s unique microlens technology enables imaging at a much higher resolution than conventional microscopy methods provide.

To advance backside optical imaging to the 11-nanometer node, the team will utilize micromirrors built by Bifano, and beam and polarization shaping techniques pioneered by Mertz to achieve the tiniest focal spot—and test these advances using a laser voltage imaging system. By focusing a laser beam on a tiny transistor and monitoring the resulting free carrier changes due to transistor switching, this system interrogates the local functionality of the circuits at the transistor level. To conduct these tests, the BU team will work with DCG Systems, a major supplier of debug, failure analysis and circuit edit equipment to the semiconductor industry for 23 years.

“Our research group has been at the forefront of high-resolution subsurface microscopy utilizing solid immersion techniques,” said Goldberg. “This is an exciting opportunity to go beyond the traditional limits, utilizing new methods with Bifano and Mertz that we hope will provide imaging resolution to enable diagnostics and analysis of 11-nanometer circuit features. Of course, new science and technology in one field can often lead to advances elsewhere, so we are actively looking to apply such high-resolution techniques to biology and potentially medical devices.”
 

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