Design Margins, Scaling and the Future of Moore’s Law
With Andrew B. Kahng
Electrical and Computer Engineering
Computer Science and Engineering
University of California, San Diego
Refreshments will be served outside Room 339 at 3:45 p.m.
Faculty Host: Ayse Coskun
Abstract: In the late CMOS era, the value of semiconductor integration faces severe challenges of power, variability and cost. The continuation of Moore’s Law through advanced manufacturing techniques, new materials, and novel device architectures is fraught with risk: leading-edge companies spend billions to enable the next technology node but can obtain only 20% improvements in power efficiency, speed, or layout density in return. In the first part of this talk, I will explain why today’s poor return on technology investment is ultimately due to margins (guardbands) in the IC design process, which are applied in light of process variations, voltage fluctuations, aging, and other perceived sources of variability. Future scaling of designs and the continuation of Moore’s Law itself, require a new, holistic management of margin – a “unified margin optimization” whereby millivolts, megahertz, nanometers, microwatts, sigmas, and square microns are flexibly traded off not only against each other but also against product-level metrics such as yield or design complexity. In the second part of the talk, I will discuss the concept of “design-based equivalent scaling.” When lithographic patterning and the electrical performance of devices and interconnects all run out of steam, it falls on design techniques (spanning layout through architecture – power and reliability management, design for manufacturability, adaptivity and resilience, etc.) to deliver the needed “equivalent scaling.” Here, communication between traditional silos is a recurring theme: “what if we could know what they were thinking.” I will give examples of how bridges between design and manufacturing, and between system design and chip implementation, can deliver design-based equivalent scaling and help perpetuate the Moore’s Law trajectory of semiconductor value.
About the Speaker: Andrew B. Kahng is a professor of Computer Science and Engineering and Electrical and Computer Engineering at the University of California, San Diego, where he holds the role of endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-97) and as founder, chairman and CTO at Blaze DFM (2004-06). He is the coauthor of three books and over 400 journal and conference papers, holds 22 issued U. S. patents, and is a fellow of ACM and IEEE. He has served as the international chair and co-chair of the design technology working group of the International Technology Roadmap for Semiconductors since 2000. His research interests include IC physical design and performance analysis, the IC design-manufacturing interface, combinatorial algorithms and optimization, and the roadmapping of systems and technology.