ECE Seminar with Wooram Lee

4:00 pm on Thursday, February 21, 2013
Photonics Center, 8 Saint Mary’s St., Room 339
A New Circuit Design Paradigm Exploiting Nonlinear Phenomena With Wooram Lee, Broadcom Faculty Host: Enrico Bellotti Refreshments will be served outside Room 339 at 3:45 p.m. Abstract: Represented by Moore's law, transistor miniaturization has been an ongoing process for more than a half century. This technology has resulted in the rapid growth of diverse computing and communication innovations. However, CMOS scaling beyond the 14-nm node is uncertain because its physical dimensions are close to atomic and quantum mechanical boundaries. Nonetheless, demands have been growing continuously for faster operation frequencies of electronic systems and a higher information transmission rate. Besides communication, numerous new applications for medicine, healthcare, entertainment, and security, among others, are also emerging, which will set new technological challenges in integrated circuits. To address these challenges beyond the limits of transistors, I have proposed a new circuit design methodology inspired by nonlinear wave propagation. This method is closely related to intriguing phenomena in other physics disciplines such as optics, fluid mechanics, and plasma physics. Based on this, in the first part of this presentation, I will propose a passive 20-GHz frequency divider for the first time implemented in CMOS. This device has close to ideal noise performance with no DC power consumption. Next, to achieve sensitivity toward the thermal noise limit, this presentation will describe a 10-GHz CMOS noise-squeezing amplifier. This amplifier enhances sensitivity of an input signal in one quadrature phase by 2.5 dB at the expense of degrading the other quadrature component. Lastly, this talk will introduce an LC lattice to generate 2.7 Vp-p, 6 ps pulses in CMOS using constructive nonlinear wave interaction. The proposed lattice exhibits the sharpest pulse width achieved for high-amplitude pulses (>1 V) in any CMOS processes. About the Speaker: Wooram Lee received his B.Sc. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 2001 and 2003, and his Ph.D degree at Cornell University in 2012. From 2003 to 2007, he was a research engineer at the Electronics and Telecommunications Research Institute (ETRI), Korea, where he worked on optical transceivers and links. In 2011, he held a summer internship at the IBM T. J. Watson Research Center, New York, where he worked on a millimeter-wave frequency multiplier in a 90 nm SiGe process. Since 2012, he has been with Broadcom, California, where he is working on multi-Gbps CMOS transceivers for broadband communication in optical, copper and backplane applications. His research interests include high-speed, low-noise electronics for applications in communication systems, sensing, and biomedical devices. Mr. Lee received the IEEE Solid-State Circuits Predoctoral Fellowship for 2010-11 and the Samsung Graduate Fellowship for 2007-2012. He was a recipient of the Best Paper Award of the IEEE Radar Conference in 2009 and the Silver Medal at the National Physics Competition in 1996.