System-level Run-time Management Techniques for Energy-efficient Silicon-Photonic Manycore Systems
The goal of this project is to develop a suite of run-time management techniques at the architectural level to manage power dissipation in silicon-photonic systems. We focus on modulator/filter localized tuning power and laser power. In particular, we are exploring workload scheduling/migration, memory mapping and dynamic voltage and frequency scaling for minimizing localized modulator/filter tuning power. For laser power we are investigating dynamic photonic resource assignment, workload scheduling and memory mapping.
Reliable and Secure VLSI nanosystems
The objective of this project is to combine low-power circuit and micro-architecture techniques with ideas from information/coding theory to tackle the device-variability problems in nanoscale systems. Our basic premise is to allow noise at the device level, rather than paying the ever-increasing energy and area costs required to keep all nanodevices well-behaved. We plan to develop the overlying VLSI architectures that exploit feedback and redundancy to maintain nearly the same end-to-end reliability and performance as today’s designs while consuming much less energy.
Biologically-inspired Robust Computing Architectures
Biological systems have natural tolerance to faults due to the underlying redundancy of their architectures. We are developing a biologically-inspired computing architecture that leverages this fault-tolerance property to adapt to the various faults that can occur in the encompassing computing system during its lifetime. In particular, we are exploring the replacement of varying granularities of computation with robust fault-tolerant neural networks.
Next Generation Solid Immersion Microscopy for Fault Isolation in Back-Side Analysis
The rapid decrease in the dimensions of integrated circuits has necessitated corresponding higher-resolution methods for fault isolation and localization. Current state-of-the-art, defect imaging systems are reaching the limits of their resolution. Our goal is to investigate the effects of decrease in the IC dimensions on fault localization measurements by modeling the interaction of highly focused optical beams and nanoscale semiconductor integrated circuits. To this end, we are building an electromagnetic model that takes into account various parameters including polarization of light, numerical aperture, doping concentration, voltage level and circuit dimensions; to obtain a simulated image of the circuit, which would then we verified against the experimental data.
Wave-pipelined Multiplexed Routing for Gigascale Integration
The main objective of this project was to develop a pervasive wire sharing technique – wave-pipelined multiplexed routing, that can be easily applied across the entire range of on-chip interconnects. A circuit-level, system-level and physical-level analysis was completed to explore the limits and opportunities to apply WPM routing to gigascale integration (GSI) systems. Design, verification and optimization of the WPM circuit and measurement of its tolerance to external noise constituted the circuit-level analysis. The physical-level study involved designing wire sharing-aware placement algorithms to maximize the advantages of WPM routing. A system-level simulator that designs the entire multilevel interconnect network was developed to perform the system-level analysis. The effect of WPM routing on a full-custom interconnect network and a semi-custom interconnect network was studied.
Carbon Nanotubes Interconnects in VLSI applications
In this project we explored the potential of using carbon nanotubes for on-chip communication. Based on the critical parameters of carbon nanotubes a methodology for interconnect sizing in terms of power, performance and area was developed. These circuit-level optimizations were then extrapolated to the system-level. At the system level the application of carbon nanotube interconnects for core-to-core communication in multi-core systems was studied. Various data routing strategies were investigated for a range of loads to identify the best possible configuration for carbon nanotubes.
Low complexity decoding algorithm for Reed-Solomon code
In this project we developed a new low-complexity chase decoding algorithm for decoding Reed-Solomon codes of various lengths. A joint optimization of the decoding algorithm and its hardware implementation was performed to develop an integrated solution.
Integrated Photonic networks for Manycore systems
The goal of this project is to develop a silicon-photonic interconnect system that can significantly improve the communication-limited throughput of manycore processors by using silicon photonics to unify the on-chip and off-chip communication into a single, energy-efficient network. This multi-team project aims to develop a complete photonic solution (device design to system design), which could potentially replace electrical interconnects for both on-chip (global) and off-chip communication. While achieving this goal, photonic link components, circuit and system design for photonic links, and simulation framework for architectural support and exploration are being developed.
Plastic neuromorphic hardware for autonomous navigation in mobile robots
The goal of this project is to develop and translate adaptive neural models into custom neuromorphic hardware for autonomous learning in sensory, motivational, planning and reinforcement circuits in mobile robots. We adopt an integrated approach based on the joint optimization of neural algorithms and hardware architectures to arrive at low-power high-performance solutions. In terms of neural modeling, we will develop efficient ego-motion estimation and reinforcement learning modules that are cognizant of the limitations of hardware implementation. Issues such as locality of computation, dynamic coding, and processing load will be addressed, resulting in models that better exploit the hardware characteristics to allow real-time processing and learning in freely behaving robotic agents.