Silicon-Photonic Networks for Manycore/GPU Systems
The high-level goal of this project is to develop a silicon-photonic interconnect system that can improve performance of manycore processors and GPUs. This project has multiple sub-projects – 1) The first sub-project focuses on developing run-time system-level power management techniques for managing laser power and thermal-tuning power of silicon-photonic networks; 2) The second sub-project focuses on designing a unified on-chip/off-chip silicon-photonic network for next generation CPU-GPU systems; and 3) The third sub-project focuses on the design of novel cross-layer design automation methods for 2.5D-integrated heterogeneous systems with silicon-photonic networks, and the demonstration of the benefits of these 2.5D systems with respect to energy efficiency, robustness, and performance.
Programmable Hardware Monitors for Security
The goal of this project is to design and implement programmable hardware monitors for securing processors. We are developing a complete framework including the hardware monitor architecture and its interface with a RISC-V processor as well as an operating system. A user can program our hardware monitors based on his/her requirements to employ them in different applications such a detecting security attacks, online profiling, and fuzzing.
Hardware Accelerators for Machine Learning
The goal of this project is to develop novel hardware accelerator architectures that can be used to accelerate both general-purpose and special-purpose applications. This effort is part of a larger project whose overarching goal is to develop Programmable Smart Machines (PSMs). PSMs are hybrid computing systems that behave as programmed but transparently learn and automatically improve their operation.
Securing CMOS Integrated Circuits Using Nanoantenna-based Optical Watermarks
The objective of this project is to develop and demonstrate optical nanoantennas as an optical watermarking technology, which can be used to rapidly detect any insertion of malicious hardware Trojans in CMOS IC chips. We propose to strategically embed predefined structures in one or more layers of the metal stack within each standard cell while developing the standard cell library. These metal nanostructures can be engineered to produce unique optical signatures that are a function of their design and surrounding environment. Any modifications in the form of replacement or re-arrangement of existing cells to add a Trojan can be detected through rapid post-fabrication backside imaging.
Designing Digital CMOS Logic Circuits using Equalization
The objective of this project is to combine low-power circuit techniques with ideas from information/coding theory to design reliable and energy-efficient digital CMOS logic circuits operating in the sub-threshold and near-threshold regime. In particular, we are exploring the use of feedback equalization techniques to dynamically change the switching threshold of the logic gates (based on the switching profiles in the previous clock cycle) in a digital sequential logic block. This dynamic change of switching threshold can be leveraged to mitigate process variation effects and/or reduce critical path delay to improve reliability and energy-efficiency of the digital sequential logic block.
Wave-pipelined Multiplexed Routing for Gigascale Integration
The main objective of this project was to develop a pervasive wire sharing technique – wave-pipelined multiplexed routing, that can be easily applied across the entire range of on-chip interconnects. A circuit-level, system-level and physical-level analysis was completed to explore the limits and opportunities to apply WPM routing to gigascale integration (GSI) systems. Design, verification and optimization of the WPM circuit and measurement of its tolerance to external noise constituted the circuit-level analysis. The physical-level study involved designing wire sharing-aware placement algorithms to maximize the advantages of WPM routing. A system-level simulator that designs the entire multilevel interconnect network was developed to perform the system-level analysis. The effect of WPM routing on a full-custom interconnect network and a semi-custom interconnect network was studied.
Carbon Nanotubes Interconnects in VLSI applications
In this project we explored the potential of using carbon nanotubes for on-chip communication. Based on the critical parameters of carbon nanotubes a methodology for interconnect sizing in terms of power, performance and area was developed. These circuit-level optimizations were then extrapolated to the system-level. At the system level the application of carbon nanotube interconnects for core-to-core communication in multi-core systems was studied. Various data routing strategies were investigated for a range of loads to identify the best possible configuration for carbon nanotubes.
Low complexity decoding algorithm for Reed-Solomon code
In this project we developed a new low-complexity chase decoding algorithm for decoding Reed-Solomon codes of various lengths. A joint optimization of the decoding algorithm and its hardware implementation was performed to develop an integrated solution.
Next Generation Solid Immersion Microscopy for Fault Isolation in Back-Side Analysis
The rapid decrease in the dimensions of integrated circuits has necessitated corresponding higher-resolution methods for fault isolation and localization. Current state-of-the-art, defect imaging systems are reaching the limits of their resolution. Our goal is to investigate the effects of decrease in the IC dimensions on fault localization measurements by modeling the interaction of highly focused optical beams and nanoscale semiconductor integrated circuits. To this end, we are building an electromagnetic model that takes into account various parameters including polarization of light, numerical aperture, doping concentration, voltage level and circuit dimensions; to obtain a simulated image of the circuit, which would then we verified against the experimental data.
Plastic neuromorphic hardware for autonomous navigation in mobile robots
The goal of this project is to develop and translate adaptive neural models into custom neuromorphic hardware for autonomous learning in sensory, motivational, planning and reinforcement circuits in mobile robots. We adopt an integrated approach based on the joint optimization of neural algorithms and hardware architectures to arrive at low-power high-performance solutions. In terms of neural modeling, we will develop efficient ego-motion estimation and reinforcement learning modules that are cognizant of the limitations of hardware implementation. Issues such as locality of computation, dynamic coding, and processing load will be addressed, resulting in models that better exploit the hardware characteristics to allow real-time processing and learning in freely behaving robotic agents.