Journal

  1. [TVLSI 2014] M. Zangeneh and A. Joshi, “Design and Optimization of Nonvolatile Multi-bit 1T1R Resistive RAM,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.22, no.8, pp.1815-1828, Aug. 2014. (pdf)
  2. [ALR 2014] F. Raudies, S. Eldridge, A. Joshi and M. Versace, “Learning to navigate in a virtual world using optic flow and stereo disparity signals,” Artificial Life and Robotics, Springer Japan Aug. 2014. (link)
  3. [JSTQE 2013] C. Chen and A. Joshi, “Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture,” Selected Topics in Quantum Electronics, IEEE Journal of, vol.19, no.2, pp.338,350, March-April 2013. (Invited paper) (pdf)
  4. [TVLSI 2012] Z. Wang, M. Karpovsky and A. Joshi, “Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.20, no.7, pp.1221-1234, July 2012. (pdf)
  5. [JETCAS 2012] C. Batten, A. Joshi, V. Stojanovic, and K. Asanovic, “Designing Chip-Level Nanophotonic Interconnection Networks,” Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol.2, no.2, pp.137-153, June 2012. (pdf)
  6. [TVLSI 2012] Z. Wang, M. Karpovsky and A. Joshi, “Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.20, no.6, pp.1036-1048, June 2012. (pdf)
  7. [MICRO 2009] C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics,” Micro, IEEE , vol.29, no.4, pp.8-21, July-Aug. 2009. (IEEE Micro Special Issue: Micro’s Top Picks from Hot Interconnects 16) (pdf)
  8. [TVLSI 2007] A. Joshi, G. Lopez and J. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, no.9, pp.990-1002, Sept. 2007.  (pdf)
  9. [TVLSI 2005] A. Joshi and J. Davis, “Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI),” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.13, no.8, pp.899-910, Aug. 2005.  (pdf)

Book Chapter

  1. [SPRINGER 2013] C. Batten, A. Joshi, V. Stojanović, and K. Asanović, “Designing Nanophotonic Interconnection Networks,” in Integrated Optical Interconnect Architectures and Applications in Embedded Systems, Springer, 2013. (link)

Technical Reports

  1. [BU 2013] F. Raudies, S. Eldridge, A. Joshi and M. Versace, “Reinforcement Learning of Visual Navigation Using Distances Extracted from Stereo Disparity or Optic Flow” (Boston University ECE-2013-1). (pdf)
  2. [UC BERKELEY 2009] S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and K. Asanovic, “Re-architecting DRAM with Monolithically Integrated Silicon Photonics” (UC Berkeley EECS-2009-179). (pdf)

Conference/Workshop

  1. [DATE 2015] T. Cilingiroglu, M. Zangeneh, A. Uyar, W. Clem Karl, J. Konrad, A. Joshi, B. Goldberg and M. Selim Unlu, “Dictionary-based Sparse Representation for Resolution Improvement in Laser Voltage Imaging of CMOS Integrated Circuits,” to appear in Proc. Design, Automation and Test in Europe (DATE) 2015.
  2. [NOCS 2014] C. Chen, T. Zhang, P. Contu, J. Klamkin, A. Coskun, and A. Joshi, “Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs,” Proc. International Symposium on Networks-on-Chip (NOCS) 2014. (pdf)
  3. [NEUROARCH-ISCA 2014] J. Appavoo, A. Waterland, S. Eldridge, K. Zhao, A. Joshi, S. Homer and M. Seltzer, ”Programmable Smart Machines: A Hybrid Neuromorphic approach to General Purpose Computation” Neuromorphic Architectures (NeuroArch) Workshop at 41th International Symposium on Computer Architecture (ISCA-41) 2014. (pdf)
  4. [GLSVLSI 2014] S. Eldridge, F. Raudies, D. Zou and A. Joshi, “Neural Network-Based Accelerators for Transcendental Function Approximation,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2014. (pdf)
  5. [DATE 2014] M. Zangeneh and A. Joshi, “Sub-threshold Logic Circuit Design using Feedback Equalization,” Proc. Design, Automation and Test in Europe (DATE) 2014. (pdf)
  6. [DATE 2014] T. Zhang, J. Abellan, A. Joshi and A. Coskun, “Thermal Management of Manycore Systems with Silicon-Photonic Networks,” Proc. Design, Automation and Test in Europe (DATE) 2014. (pdf)
  7. [SHAW-HPCA 2014] C. Chen, A. Joshi and E. Salminen, “Profiling EEMBC MultiBench Programs using Full-system Simulations,” Proc. Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-5) at 20th International Symposium On High Performance Computer Architecture (HPCA-20) 2014. (pdf)
  8. [ISLPED 2013] Z. Takhirov, B. Nazer and A. Joshi, “Energy-Efficient Pass-Transistor-Logic Using Decision Feedback Equalization,” Proc. International Symposium on Low Power Electronics and Design (ISLPED) 2013. (pdf)
  9. [BIC-ISCA 2013] S. Eldridge, F. Raudies and A. Joshi, “Approximate Computation using Neuralized FPU,” Brain-Inspired Computing (BIC) Workshop at 40th International Symposium on Computer Architecture (ISCA-40) 2013. (pdf)
  10. [LGDMA-IGCC 2012] A. Joshi, C. Chen, Z. Takhirov and B. Nazer, “A Multi-layer Approach to Green Computing: Designing Energy-efficient Digital Circuits and Manycore Architectures,” Proc. Workshop on Lighter-than-Green Dependable Multicore Architectures (LGDMA), Held in conjunction with International Green Computing Conference (IGCC) 2012. (Invited paper) (pdf)
  11. [ICCNS 2012] M. Motter, M. Versace, and A. Joshi, “Neuromorphic solutions for UAS collision avoidance,” Proc. International Conference on Cognitive and Neural Systems (ICCNS) 2012.
  12. [GLSVLSI 2012] M. Zangeneh and A. Joshi, “Performance and Energy Models for Memristor-based1T1R RRAM Cell,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2012. (pdf)
  13. [ISQED 2012] Z. Takhirov, B. Nazer and A. Joshi, “Error Mitigation in Digital Logic using Feedback Equalization with Schmitt Trigger (FEST) Circuit,” Proc. International Symposium on Quality Electronic Design (ISQED) 2012. (pdf)
  14. [ALLERTON 2011] Z. Takhirov, B. Nazer and A. Joshi, “A Preliminary Look at Error Avoidance in Digital Logic Via Feedback Equalization,” in Proc. Allerton-11 2011. (Invited paper) (pdf)
  15. [HOTI 2011] C. Chen, J. Meng, A. Coskun and A. Joshi, “Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems,”  in Proc. High-Performance Interconnects (HOTI) 2011. (pdf)
  16. [GLSVLSI 2011] Z. Wang, M. Karpovsky and A. Joshi, “Influence of Metallic Tubes on the Reliability of CNTFET SRAMs: Error Mechanisms and Countermeasures,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011. (pdf)
  17. [GLSVLSI 2011] J. Meng, C. Chen, A. Coskun and A. Joshi, “Run-Time Energy Management of Manycore Systems Through Reconfigurable Interconnects,” Proc. Great Lakes Symposium on VLSI (GLSVLSI) 2011. (pdf)
  18. [ISCA 2010] S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic, K. Asanovic, “Re- Architecting a DRAM Memory Channel with Monolithically Integrated Silicon Photonics,” Proc. International Symposium on Computer Architecture (ISCA) 2010 (pdf)
  19. [DSN 2010] Z. Wang, M. Karpovsky, A. Joshi, “Reliable MLC NAND Flash Memories Based on nonlinear t-Error-Correcting Codes”, Proc. 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2010 (pdf)
  20. [OFC 2010] V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen, and K. Asanovic, “Design-space exploration for CMOS photonic processor networks,” Optical Fiber Communication (OFC), collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC) , vol., no., pp.1-3, 21-25 March 2010 (pdf)
  21. [WTM 2010] V. Stojanovic, A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, S. Chen and K. Asanovic, “CMOS photonic processor-memory networks,” Photonics Society Winter Topicals Meeting Series (WTM), 2010 IEEE , vol., no., pp.118-119, 11-13 Jan. 2010 (pdf)
  22. [ICICSP 2009] Z. Wang, M. Karpovsky, B. Sunar, and A. Joshi, “Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes,” Proc. Int. Conf. on Information, Communications and Signal Processing, Dec. 2009 (pdf)
  23. [PICA-MICRO 2009] A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics” Workshop on Photonic Interconnects & Computer Architecture. Held in Conjunction with 42nd Annual ACM/IEEE International Symposium on Microarchitecture, MICRO-42 2009(pdf)
  24. [LEOS 2009] A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Designing Manycore Processor Networks using Silicon Photonics,” Proc. IEEE/Photonics Society Annual Meeting 2009. (pdf)
  25. [HOTI 2009] A. Joshi, B. Kim and V. Stojanovic, “Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects,” Proc. IEEE Symposium on High-Performance Interconnects, Aug 2009. (pdf)
  26. [ICS 2009] S. Beamer, K. Asanović, C. Batten, A. Joshi, and V. Stojanović, “Designing Multi-socket Systems Using Silicon Photonics”, Proc. 23rd International Conference on Supercomputing (ICS-09), Yorktown Heights, NY, June 2009. (pdf)
  27. [CLEO 2009] V. Stojanovic, A. Joshi, C. Batten, J. Kwon and K. Asanovic, “Manycore Processor Networks with Monolithic Integrated CMOS Photonics,” Proc. CLEO 2009 (Invited paper) (pdf)
  28. [NOCS 2009] A. Joshi, F. Chen and V. Stojanovic, “A Modeling and Exploration Framework for Interconnect Network Design in the Nanometer Era,” 3rd IEEE/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009. (pdf)
  29. [NOCS 2009] A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd IEEE/ACM International Symposium on Network-on-Chip (NOCS-3), May 2009 (Nominated for Best Paper Award)(pdf)
  30. [HOTI 2008] C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kaertner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics”, Proc. 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects 2008), Stanford, CA, August 2008. (pdf)
  31. [NANONETS 2007] F. Chen, A. Joshi, V. Stojanovic and A. Chandrakasan, “Scaling and Evaluation of Carbon Nanotube Interconnects for VLSI Applications,” Proc. Nanonets 2007. (pdf)
  32. [IITC 2006] D. Sekar, R. Venkatesan, K. Bowman, A. Joshi, J. Davis and J. Meindl, “Optimal repeaters for sub-50nm interconnect networks,” Proc. IITC 2006, pp. 199-201. (pdf)
  33. [VLSI Design 2006] A. Joshi, V. Deodhar and J. Davis, “Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing,” Proc. VLSI Design 2006, pp. 773-776. (pdf)
  34. [AMC 2005] J. Davis, V. Deodhar and A. Joshi, “The Impact of Wave Pipelining on Future Interconnect Technologies,” Proc. AMC 2005 (Invited paper). (pdf)
  35. [SOCC 2005] A. Joshi and J. Davis, “Gigascale ASIC/SoC Design using Wave-Pipelined Multiplexed (WPM) Routing,” Proc. IEEE-SOCC 2005, pp. 139-142. (pdf)
  36. [GLSVLSI 2005] A. Joshi and J. Davis, “Wave-Pipelined 2-Slot Time Division Multiplexed (WP/2-TDM) Routing,” Proc. GLSVLSI 2005, pp.446-451. (pdf)
  37. [SLIP 2004] A. Joshi and J. Davis, “A 2-Slot Time-Division Multiplexing (TDM) Interconnect Network for Gigascale Integration (GSI),” Proc. IEEE/ACM SLIP Workshop 2004, pp. 64-68. (pdf)