ECE MS Thesis Defense Kiran Thanjavur

  • Starts: 11:00 am on Friday, April 21, 2017
  • Ends: 1:00 pm on Friday, April 21, 2017
Title: AUTOMATIC GENERATION OF HARDWARE TREE CLASSIFIERS Abstract: Machine Learning is growing in popularity and spreading across different fields for various applications. Due to this trend, machine learning algorithms use different hardware platforms and are being experimented to obtain high test accuracy and throughput. FPGAs are well-suited hardware platform for machine learning because of its re-programmability and lower power consumption. Programming using FPGAs for machine learning algorithms requires substantial engineering time and effort compared to software implementation. We propose a software assisted design flow to program FPGA for machine learning algorithms using our hardware library. The hardware library is highly parameterized and it is written using Chisel. As of now, our library consists of the components required to implement decision trees and random forests. The software assisted design and the hardware library can be expanded to accommodate other machine learning algorithms in the future.
Location:
PHO, 6-8 St. Mary’s Street (404/428)

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