As the rate of scaling of CMOS technology, used in microprocessors and other digital systems, decreases, researchers are increasing the number of processing cores on a chip with hopes of sustaining the historic performance improvement of VLSI systems through parallelism. Current systems already have dozens of cores on a single chip, and this number is expected to be in the hundreds, maybe even thousands, in the future. However, the envisioned performance improvement that comes with increasing the core count could be limited by the on-chip communication bandwidth.
Boston University’s Assistant Professor Ajay Joshi (ECE) is hoping to solve this problem by using photonic link technology for communication on the manycore chip. Specifically, he’d like to investigate how we can use this technology in manycore systems with thousands of cores on a single die.
The Defense Advanced Research Projects Agency (DARPA), a branch of the U.S. Department of Defense, recently awarded Joshi nearly $300K to pursue this project, titled “Electro-photonic network-on-chip architectures in 1000+ core systems.”
“Part of what I’m tasked to do is determine what kind of applications could be run on 1000+ core systems and then see if and how photonics can be utilized to maximize manycore system energy efficiency,” said Joshi of the grant. He believes that in manycore systems, electro-photonic networks may prove to be a better solution than purely photonic or electrical networks.
Joshi’s research interests include on-chip and off-chip interconnect design; digital/analog circuit design; and computer architecture.
Earlier this year, Joshi also received a NSF CAREER award to develop system-level run-time techniques to manage laser power and thermal tuning power in silicon-photonic networks.
-Rachel Harrington (firstname.lastname@example.org)
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