Research Spotlight Archive

Back to Research Spotlight

Title: Design of Reliable and Secure Hardware Resistant to AttacksHardware resistant to attacks

Participants: Prasanna Rao (MS ’10), Zhen Wang (PhD ’11), and Professor Mark Karpovsky

Funding: National Science Foundation (NSF)

Background: Cryptographic algorithms are designed so that by observing only the inputs and outputs of the algorithm, it is computationally infeasible to break the cipher or equivalently determine the secret key used in encryption and decryption. Thus, the algorithm itself does not leak enough useful information during its operation to compromise its security. However, when a physical implementation of the algorithm is considered, additional information like power consumption, behavior as a result of internal faults, and timing of the circuit implementing the algorithm can provide enough information to compromise the security of the system. This type of data can now be readily gathered since cryptographic hardware (smart cards, SIM cards, USB tokens, Trusted Platform Modules in smartphones) is accessible to anyone. Attacks based on the use of this implementation-specific-information are known as Side Channel Attacks (SCA). Contrary to traditional cryptanalysis attacks, examples show that a  very small amount of side-channel information is enough to completely break a cryptosystem.

Description: The goal of the project is to develop methods and designs to make such attacks infeasible and to design reliable and secure memories, computational components, and cryptographic blocks for smartphones based on these methods.

Results: We are developing special robust error detecting codes which can detect any errors which may be injected by an attacker as a part of a Side-Channel Attack. As opposed to the well known codes used for communication these new robust codes have uniformly distributed error detecting capabilities. We investigate efficient encoding and decoding algorithms for thess codes and their hardware implementations. We design reliable and secure basic hardware components such as multipliers, memories as well as hardware for private key and public key cryptographic devices resistant to attacks. Architectures of these devices are based on the proposed robust error detecting codes and corresponding decoding algorithms. The proposed techniques provide for minimization of information leakage and automatic detection of an attack and disabling of the compromised hardware.


Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36