Ajay Joshi

Honors, Awards, and Editorships

• Intel Recognition Award, 2003

Classes Taught

• EC571 VLSI Principles and Applications

Research Interests

• On-chip and off-chip interconnect design
• Digital logic design
• Physical design
• Computer architecture

Selected Publications

• A. Joshi and J. Davis, “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI),” IEEE Trans. VLSI Systems, vol. 13, no. 8, pp. 899-910, Aug 2005.
• A. Joshi, G. Lopez and J. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed (WPM) Routing,” IEEE Trans. VLSI Systems, vol. 15, no. 9, pp. 990-1002, Sep 2007.
• A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd International Symposium on Network-on-Chip (NOCS-3), pp. 124-133, May 2009.
• A. Joshi, B. Kim and V. Stojanovic, “Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects,” Proc. IEEE Symposium on High-Performance Interconnects, pp. 3-12, Aug 2009.
• C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics,” IEEE Micro Special Issue: Micro’s Top Picks from Hot Interconnects 16, pp. 8-21, July/Aug 2009.