Ajay Joshi

A-JoshiAssistant Professor
PhD, Georgia Institute of Technology, 2006

Computer Engineering

Boston University Photonics Center
Boston University Center for Computational Neuroscience and Neural Technologies

(617) 353-4840
office: PHO 334
office hours: contact for appointment

Honors, Awards, and Editorships

  • 2014 ECE Award for Excellence in Teaching
  • 2012-13 Associate Editor, Journal of Circuits, Systems and Computers
  • 2012 NSF CAREER Award
  • 2011 Dean’s Catalyst Award, College of Engineering, Boston University
  • 2003 Intel Recognition Award

Classes Taught

  • EK 131/132 Introduction to Engineering
  • EC311 Introduction to Logic Design
  • EC571 VLSI Principles and Applications
  • EC 772 VLSI Graduate Design Project

Research Interests

  • Digital/analog circuit design
  • Computer architecture
  • Silicon photonics
  • Neuromorphic systems

Selected Publications

  • C. Chen, T. Zhang, P. Contu, J. Klamkin, A. Coskun, and A. Joshi, “Sharing and Placement of On-chip Laser Sources in Silicon-Photonic NoCs,” Proc. International Symposium on Networks-on-Chip (NOCS) 2014.
  • M. Zangeneh and A. Joshi, “Sub-threshold Logic Circuit Design using Feedback Equalization,” Proc. Design, Automation and Test in Europe (DATE) 2014.
  • T. Zhang, J. Abellan, A. Joshi and A. Coskun, “Thermal Management of Manycore Systems with Silicon-Photonic Networks,” Proc. Design, Automation and Test in Europe (DATE) 2014.
  • C. Chen and A. Joshi, “Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture,” Selected Topics in Quantum Electronics, IEEE Journal of, vol.19, no.2, pp.338,350, March-April 2013.
  • M. Zangeneh and A. Joshi, “Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM,” to appear in Very Large Scale Integration (VLSI) Systems, IEEE Transactions on.
  • C. Batten, A. Joshi, V. Stojanovic, and K. Asanovic, “Designing Chip-Level Nanophotonic Interconnection Networks,” Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol.2, no.2, pp.137-153, June 2012.
  • S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic, K. Asanovic, “Re- Architecting a DRAM Memory Channel with Monolithically Integrated Silicon Photonics,” Proc. International Symposium on Computer Architecture (ISCA) 2010.
  • C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic, “Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics,” IEEE Micro Special Issue: Micro’s Top Picks from Hot Interconnects 16, pp. 8-21, July/Aug 2009.
  • A. Joshi, B. Kim and V. Stojanovic, “Designing Energy-efficient Low-Diameter On-chip Networks with Equalized Interconnects,” Proc. IEEE Symposium on High-Performance Interconnects, pp. 3-12, Aug 2009.
  • A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic and V. Stojanovic, “Silicon-Photonic Clos Networks for Global On-Chip Communication,” 3rd International Symposium on Network-on-Chip (NOCS-3), pp. 124-133, May 2009.
  • A. Joshi, G. Lopez and J. Davis, “Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed (WPM) Routing,” IEEE Trans. VLSI Systems, vol. 15, no. 9, pp. 990-1002, Sep 2007.
  • A. Joshi and J. Davis, “Wave-Pipelined Multiplexed (WPM) Routing for Gigascale Integration (GSI),” IEEE Trans. VLSI Systems, vol. 13, no. 8, pp. 899-910, Aug 2005.