ECE Colloquium with André DeHon

Starts:
4:00 pm on Tuesday, October 23, 2012
Location:
Photonics Center, 8 Saint Mary’s St., Room 339
URL:
http://www.bu.edu/ece/files/2012/10/DeHon_10-23-12.pdf
Semiconductor Life Extensions Through Reconfiguration (Using Reconfiguration and Adaptivity to Deal with Variation, Aging, and Power Reduction)

With Professor André DeHon
Department of Electrical and Systems Engineering
University of Pennsylvania

Refreshments will be served outside Room 339 at 3:45 p.m.
Faculty Host: Martin Herbordt

Abstract: As we continue to scale silicon technologies, the statistical behavior of individual dopants, atoms, and bonds leads to an increased rate of defects, high variation in device characteristics, and increased changes in the characteristics of devices during in-field operation. Advanced integrated circuits will be like snowflakes – each unique and changing throughout its lifetime. Adding static margins to tolerate high device variance and potential device degradation prevents aggressive voltage scaling to reduce energy. Post-fabrication configuration in reconfigurable components, such as FPGAs, provides an opportunity to avoid the high costs of static margins. Rather than assuming worst-case device characteristics, we can deploy devices based on their fabricated or aged characteristics. This allows us to place the high-speed/leaky devices as needed on critical paths and slower/less-leaky devices on non-critical paths. As a result, it becomes possible to meet system timing requirements at lower voltages than conservative margins. Furthermore, we can reassign computations to devices in the field as device characteristics change – extending the lifetime of individual components. As the magnitude of aging effects increase, the mapping of functions to resources becomes an adaptive process that is continually refined in-system, throughout the lifetime of the component. Preliminary estimates suggest we can at least reduce energy by a factor of two without changing FPGA architectures or a factor of three with suitable device sizing, and this extends minimum energy reduction by at least one process generation.

About the Speaker: André DeHon received his S.B., S.M., and Ph.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1990, 1993, and 1996, respectively. From 1996 to 1999, André co-ran the BRASS group in the Computer Science Department at the University of California at Berkeley. From 1999 to 2006, he was an Assistant Professor of Computer Science at the California Institute of Technology. Since 2006, he has been an Associate Professor of Electrical and Systems Engineering at the University of Pennsylvania. He is broadly interested in how we physically implement computations from substrates, including VLSI and molecular electronics, up through architecture, CAD, and programming models. He places special emphasis on spatial programmable architectures (e.g. FPGAs) and interconnect design and optimization.