Yeni Sayfa 1
 
 
 
 
 


 

acoskun(at)bu.edu
 

 
 

Phone:
(617) 358-3641 (Office)


 

 

Fax:
(617) 353-7337

 
 

Address:
Boston University
ECE Department
8 St. Mary's Street
Boston, MA 02215
 

 
 

Office:
PHO 336

 


 

 

 

 

 
  .Ayse Kivilcim Coskun

Click here for the file (pdf updated Dec'13).


Education:

 


PhD Computer Science and Engineering,
University of California, San Diego 2009

MS Computer Science and Engineering, University of California, San Diego 2006

BS Microelectronics Engineering, Minor Degree in Physics, Sabanci University, Turkey 2003
 

Research Interests:

 


Green computing, multi/manycore architectures, thermal and energy management, 3D stacked architectures, computer architecture, cyber-physical systems, embedded system and software design.

 

Work Experience:

 


Boston University, Boston, MA
Assistant Professor in Electrical and Computer Engineering Department September 2009-present

Tenure-track faculty with research, teaching, and service duties.
Classes taught: Introduction to Embedded Systems (EC535), Introduction to Software Engineering (EC327), Advanced Computing Systems & Architecture (EC700).


University of California San Diego, San Diego, CA
Graduate Student Researcher in Computer Science and Engineering Department October 2003-September 2009

Advisor: Tajana Simunic Rosing
PhD Thesis: "Efficient Thermal Management for Multiprocessor Systems".

Sun Microsystems, San Diego, CA
Intern in Systems Dynamics Characterization and Control Team June 2006-June 2008, October 2008-September 2009
Supervisor: Kenny C. Gross
Conducted research on temperature and reliability modeling / management methods, monitoring real-time system behavior, and runtime analysis. Contributed to 6 issued and pending patents.

Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
Intern in Microelectronic Systems Laboratory June 2008-September 2008

Advisors: Prof. Yusuf Leblebici and Prof. Giovanni de Micheli
Conducted research on thermal modeling and dynamic thermal management of 3D circuits.

Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland
Intern in Microelectronic Systems Laboratory June 2005-September 2005

Advisors: Prof. Yusuf Leblebici and Prof. Giovanni de Micheli
Developed a simulation and analysis framework for evaluating multiprocessor system-on-a-chip reliability.

 

Grants & Awards:

 


*I have worked with a number of government labs and industry partners, including Sandia Labs, VMware, Oracle, AMD, and others. Please see the pdf version (above) for an updated list of grants.

NSF CAREER Award, 3D Stacked Systems for Energy-Efficient Computing: Innovative Strategies in Modeling and Runtime Management, 2012-2017.

Best Paper Award, High Performance Embedded Computing (HPEC) Workshop, September 2011.

A. Richard Newton Graduate Scholarship Award, Design Automation Conference (DAC), 3D Systems for Low-Power High-Performance Computing, June 2011.

Deanís Catalyst Award at College of Engineering, Boston University for the project Green Computing through Software Optimization, May 2010.

Best Paper Award, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2009.

UCSD Graduate Student Fellowship, 2003.

Sabanci University Merit Scholarship, 1999-2003.

 

Professional Activities:

 


Conference organization:

  • Topic chair (Green Computing Systems), Design Automation and Test in Europe (DATE), 2014.

  • Topic co-chair (Green Computing Systems), Design Automation and Test in Europe (DATE), 2012-2013.

  • Proceedings chair, ACM Great Lakes Symposium on VLSI (GLSVLSI), 2013.

  • Local participation chair, IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2013.

  • Program co-chair, IFIP/IEEE VLSI-SoC 2012.

  • Track co-chair, Design Automation and Test in Europe (DATE), Computing and Green IT Systems Track, 2012.

  • Program co-chair, International Workshop on Adaptive Power Management with Machine Intelligence (APMMI), in conjunction with ICCAD, 2011.

  • Workshop co-chair, Thermal modeling and Management: Chips to Datacenters Workshop, in conjunction with IEEE International Green Computing Conference (IGCC), 2011.

  • Special session co-chair, IFIP/IEEE VLSI-SoC 2010.

Technical program committee member:

  • I have been a TPC member for several conferences (mostly in design automation) such as DAC, DATE, GLSVLSI, VLSI-SoC, IPDPS, and others.

  • The pdf version above provides a detailed list.

Reviewer for IEEE Transactions on VLSI, IEEE Transactions on CAD, IEEE Transactions on Embedded Systems, and for conferences such as DATE, DAC, ICCAD, and ISCA.

IEEE and ACM Member.