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- Art Education Thesis ExhibitionAll day
- MFA Thesis Exhibition: Painting & Sculpture IIAll day
- MFA Thesis Exhibition: Graphic DesignAll day
- Last Day of Spring 2019 ClassesAll day
- An Evening with Berta Rojas (Concert & Reception)5:00 am
- Moments In Time8:00 am
- GRS Dissertation Defense of Lilian Jaimes Arellano8:30 am
- Yom HaShoah - Holocaust Remembrance Day - Reading of the Names9:00 am
- Liquid Fun Presents: The Graduate9:00 am
- Boston University's Information Security Annual Spring Shred Event10:00 am
- Challah For Hunger - Selling Challah! 11:00 am
- Sociology Department Seminar: The College Economy: How Students Manage Everyday Inequalities12:00 pm
- Drop-In Writing Assistance 12:00 pm
- Bioinformatics Sponsored Systems Biology Seminar12:45 pm
- ECE MS Thesis Defense Announcement: Sahan Lakshitha Bandara3:00 pm
- Ethics Seminar- Agnes Callard4:00 pm
- Inference from Multivariate Respondent-Driven Sampling Data (Krista Gile - UMass Amherst)4:00 pm
- Creating Outdoor Spaces that Connect Children to the Natural World4:30 pm
- Therapy Dogs @Mugar5:00 pm
- Latin American Studies Reception Featuring Performance by Berta Rojas5:00 pm
- Piano Ensemble Concert6:00 pm
- Jazz Fest7:00 pm
- HORIZON LINE7:30 pm
- MAINSTAGE OPERA: The Cunning Little Vixen by Leoš Janáček 7:30 pm
- BLUETS: A LECTURE IN SIX FUGUES7:30 pm
- THE LATHE OF HEAVEN7:30 pm
ECE MS Thesis Defense Announcement: Sahan Lakshitha Bandara
Thesis Title: Investigating the Viability of Adaptive Caches as a Defense Mechanism Against Cache Side-Channel AttacksAbstract: The ongoing miniaturization of semiconductor manufacturing technologies has enabled the integration of tens to hundreds of processing cores on a single chip. Unlike frequency-scaling where performance is increased equally across the board, core-scaling, and hardware thread-scaling harness the additional processing power through the concurrent execution of multiple processes or programs. This approach of mingling or interleaving process executions has engendered a new set of security challenges that risks to undermine nearly three decades worth of computer architecture design efforts.The complexity of the runtime interactions and aggressive resource sharing among processes, e.g., caches or interconnect network paths, have created a fertile ground to mount attacks of ever-increasing acuteness against these computer systems. One such class of attacks is cache side-channel attacks.While caches are vital to the performance of current processors, they have also been the target of numerous side-channel attacks. As a result, a few cache architectures have been proposed to defend against these attacks. However, these designs tend to provide security at the expense of performance, area, and power. Therefore, the design of secure, high-performance cache architectures is still a pressing research challenge.In this thesis, we examine the viability of self-aware adaptive caches as a defense mechanism against cache side-channel attacks. We define an adaptive cache as a caching structure with (i) run-time reconfiguration capability, and (ii) intelligent built-in logic to monitor itself and determine its parameter settings. Since the success of most cache side-channel attacks depend on the attacker’s knowledge of the key cache parameters such as associativity, set count, replacement policy, among others, an adaptive cache can provide a moving target defense approach against many of these cache side-channel attacks.Therefore, the hypothesis that we investigate under this research effort is that the runtime changes in certain cache parameters should render some of the side-channel attacks less effective due to their dependence on knowing the exact configuration of the caches.Advisor: Professor Michel Kinsy, ECECommittee: Professor Martin Herbordt, ECE; Professor Tali Moreshet, ECE
When | 3:00 pm to 4:00 pm on Thursday, May 2, 2019 |
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Location | PHO 404 |