Computer Architecture and Automated Design Lab

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Principal Investigator

 

Research Assistants

 

Alumni

 
  • Martin Herbordt

 

   
  • Jiayi Sheng
  • Chen Yang

Principal Investigator

    

Research Assistants

Martin Herbordt's picture

 

Jiayi's picture

 

Chen's picture

 

Martin Herbordt

 

Jiayi Sheng

 

Chen Yang

Biography

 

Jiayi Sheng joined this lab in September 2012 and is currently working on using the concept of offline routing to accelerate HPC applications on multi-node FPGA's and designing on-chip switch architectures that can accomplish low-overhead inter-node communication. He came from Jiangxi Province of China and received his B.S. degree from Fudan University, majoring in Microelectronics in June 2012. Jiayi worked for MediaTek and Cisco as an intern respectively during the summer in 2013 and 2011

 

Chen Yang joined this lab in September 2014 and is currently working on applying compressed sensing algorithm on FPGA. He came from Shandong Province of China and received his Bachelor of Engineering and Master of Science degrees in Electrical Engineering from Wuhan University, China in 2012 and in Computer Engineering from University of Florida in 2014 respectively. Chen worked for Cadence Design System Inc. as an intern respectively during the spring and summer in 2014.

Alumni

    2014
Raphael
Landaverde
M.S. 2014
Raphael's picture   Hansen
Zhang
M.S. 2014
Hansen's picture  

Raphael joined the lab in September 2012. His research revolves around finding potential GPU based optimizations for existing Molecular Docking and Energy Minimization code. This work builds upon the PhD work of Bharat Sukhwani. Raphael received his BS in Biomedical Engineering from Boston University is 2012. Raphael worked for Microsoft in the Summer of 2013.

 

Hansen graduated from Boston University in May 2014 with MS in Computer Engineering. Previously, he received his undergraduate degree in Electrical Engineering from Fudan University in Shanghai, China in 2012. Hansen accepted a PHD Offer in the Computer Science department at Princeton University.

    2013
      2012
      2011
Atabak
Mahram
Ph.D. 2013
Atabak's picture   Ashfaq
Khan
Ph.D. 2012
Ashfaq's picture   Matt
Chiu
Ph.D. 2011
Matt's picture   Vyas
Venkataraman
Ph.D. 2011
Vyas's picture

Atabak received his Bachelor's degree in Computer Engineering from Sharif University of Technology, Iran in 2004, and his Master's degree in Computer Engineering from Amirkabir University of Technology, Iran in 2007. Atabak was a PhD student at Computer Architecture and Automated Design Lab at Boston University. He joined the lab in Summer of 2009. Atabak worked on FPGA based acceleration of Bioinformatics and Computational Biology tools and algorithms.

 

Ashfaq joined the lab in September 2008 and worked on FPGA and multi-core applications for Bio-informatics and Computational Biology, especially Discrete Molecular Dynamics. He received his Bachelor of Engineering and Master of Engineering degrees in Electronic Engineering from Tohoku University, Japan in 2004 and 2006 respectively. Before joining the lab, Ashfaq worked for Sony Corporation, Japan from April 2006 to August 2008. His job responsibilities included developing embedded software and simulator for the Cell processor. Ashfaq received The Tohoku University President's Award in 2004 and The Boston University College of Engineering Dean's Fellowship Award in 2008.

 

Shihchin "Matt" joined the lab in September 2007 and worked on developing FPGA applications for Bioinformatics and Computational Biology, especially Molecular Dynamics. From 2001 to 2005 Matt was a circuit design engineer at Sun Microsystems where he designed SRAM and custom circuits for the Gemini and Niagara processors. He received his MSEE from the University of Southern California in 2001 and his BS in Physics from National Chung Hsing University, Taiwan in 1997. Matt was awarded the ECE Prize at the 2007 BU ECE Day, and in 2006 was named Outstanding Graduate Teaching Fellow for the College of Engineering.

 

Vyas previously worked on high-level modeling and synthesis methodology for concurrent systems using rendezvous. Now he is a software engineer at Nvida Inc. He once worked at Freescale Semiconductor at 2008 as a Student Technical Intern.

    2010
      2009
Bharat
Sukhwani
Ph.D. 2010
Bharat's picture Huaxin
Dai
M.S. 2010
Huaxin's picture   Jin
Park
Sr. Research Assoc. 2008-2009
Jin's picture Yunfei
Qiu
M.S. 2009
Yunfei's picture

Bharat completed his Ph.D dissertation titled Accelerating Molecular Docking and Binding Site Mapping using FPGAs and GPUs under Dr. Herbordt in 2010. Previously, he received his Bachelor of Engineering degree in Electronics Engineering from the University of Mumbai, India in 2001 and his Master of Science degree in Electrical and Computer Engineering from the University of Arizona, Tucson in 2005. Upon completion of his PhD, Bharat accepted the Research Staff Member position at IBM T. J. Watson Research Center in Yorktown Hts., NY.

Huaxin graduated from Boston University in May 2010 with MS in Electrical and Computer Engineering. Previously, he received his Bachelor's degree in Electrical Engineering from Beijing Jiaotong University in China. Huaxin accepted a position at Immedia Semiconductor.

 

Jin was a postdoctoral researcher at the CAAD lab from January 2008 to December 2009. Before joining the lab, he had been an assistant professor in Computer Science Department at State University of New York at New Paltz (1999-2007) after receiving his Ph.D. degree from Oklahoma State University in 1998. Jin accepted a postdoctoral researcher position in the Computational Biology and Bioinformatics department at the University of Southern California

Yunfei graduated from Boston University in May 2009 with a Master of Science degree in Computer Engineering. Previously, Yunfei received his bachelor degree in Electrical Engineering from Shanghai Jiao Tong University in 2006. Yunfei accepted a position at Cavium Networks

    2008
      2007
Yongfeng
Gu
Ph.D. 2008
Yongfeng's picture Tony
Dean
M.S. 2008
Tony's picture George
Bishop
B.S. 2007
George's picture   Francois
Kosie
M.S. 2007
  Josh
Model
M.S. 2007
Josh's picture

Yongfeng (Maple) completed his Ph.D dissertation titled FPGA Acceleration of Molecular Dynamics Simulations under Dr. Herbordt in 2008. Previously, he received his undergraduate degree in Computer Science from Fudan University in Shanghai, China in 2000 and his Masters degree in Computer Science from the same university in 2003. Yongfeng is currently working at The Mathworks in Natick, MA

Tony graduated from Boston University in May 2008 with MS in Computer Systems Engineering. Previously, he received a Masters of Arts in Biology Teaching from Fitchburg State College in 2001 and a BA in Biology with a Marine Science Specialty from Boston University in 1995. Tony is currently working as a software developer at General Dynamics C4 Systems in Needham.

George received his BS degree in Electrical Engineering from Boston University in 2007. During his undergraduate career, he did internships at Burnham Engineering in Lancaster, PA and New York City Transit in New York, NY. George is currently working at Lockheed Martin

 

Francois received his MS degree from Boston University in 2007. He is currently working at Teradyne

Josh graduated from Boston University in May 2007 with a Master's in Computer Systems Engineering. He previously earned a BSE in Electrical Engineering from Princeton University in 2001. Since then he has spent his time at MIT Lincoln Laboratory working on satellite and RF communications, FPGAs, and charged particle detectors. Josh returned to Linconl Labs after finishing his MS.

    2006
Tom
VanCourt
Ph.D. 2006
Tom VanCourt's picture Doug
DiSabello
M.S. 2006
Doug DiSabello's picture Chiaochi
Huang
M.S. 2006
Chiaochi Huang's picture Matt
Graham
B.S. 2006
Matt Graham's picture

Tom completed his dissertation, titled LAMP: Tools for Creating Application-specific FPGA Coprocessors, under Prof. Herbordt in 2006. He previously earned his M.S. (2001) in Computer Science at Boston Unoversity's Metropolitan College, where he was awarded the Metropolitan College Award for Excellence in Graduate Study, and his B.S. (1978) in engineering at Cornell University. Tom is currently working at Altera in Santa Cruz, developing software tools for accelerating FPGA computations.

Doug graduated from Boston University in May 2006 with a Master's in Computer Systems Engineering. He previously earned a BS in Electrical Engineering from Boston University in May 2004. He has been a member of the CAAD Laboratory since 2003. His main research area focusses on fault tolerance methods for SRAM based FPGAs. Doug completed his M.S. in 2006.

Chiaochi completed her Master's program under Prof. Herbordt in 2006. Her work centered on FPGA implementation of Bayesion networks analysis for exploring gene regulatory networks. She previously received her Bachelor's degree from Feng Chia University's department of Information Engineering and Computer Science, in Taiwan. After MS, Chiaochi joined Marvell.

Matt has completed his B.S in Boston University's Electrical Engineering program. He worked under Professor Herbordt in the UROP (Undergraduate Research Opportunities) Program, investigating special purpose computing structures for problems in biology and chemistry. He was a member of BU's Engineering Scholars Program and a recipient of the 2004 Stratus Scholarship.

    2004-2005
Dr. Khaled
Benkrid
Visiting
Scientist
Khaled's picture Dan
Brunina
M.S. 2005
Dan's picture Vikas
Mundada
M.S. 2005
Vikas Mundada's picture Samir
Belkacemi
Visiting Scholar
Samir Belkacemi's picture Al
Conti
B.S. 2004
Al Conti's picture

Dr. Benkrid visited the lab during June and July 2005. He is a Lecturer at the University of Edinburgh, UK. His research interests include Electronic Design Automation, Hardware Compilation, Custom Computing using FPGAs and Image and Video Processing.

Dan was a master's student in Computer Systems Engineering with a concentration in computer architecture and hardware. Dan received his Masters' degree in Computer Systems Engineering from Boston University in May 2005. On leaving the CAAD lab, Dan accepted a position at IBM.

Vikas was a master's student in Computer Systems Engineering, graduating in May 2005, with his concentration in hardware and computer architecture. He received his bachelor's degree in Electrical Engineering from the University of Houston in August 2003. Vikas has accepted a position at Raytheon.

Samir was a Visiting Scholar at the CAAD lab at Boston University during 2004. He acquired his PhD (2005) in Computer Science at Queen's University of Belfast (United Kingdom), on High Level Hardware Description Environment for FPGA-Based High Performance Computing. Samir is currently working at Lattice Semiconductor.

Al graduated from Boston University in 2004 with a bachelor's degree in Computer Systems Engineering. Al's work focused on hardware design for string matching and repetitive structure detection. He received his master's degree from Northeastern University working in the Rapid Prototyping laboratory with Dr. Miriam Leeser. Al is currently working at Mitre.


Atabak Mahram PhD 2013 FPGA Acceleration of Sequence Analysis Tools in Bioinformatics
Ben Humphries MS 2013 Using Offline Routing to Implement the 3D FFT in a Multinode FPGA System
Ashfaq Khan PhD 2012 Scalable Molecular Dynamics Simulation Using FPGAs and Multicore Processors
Vyas Venkataraman PhD 2011 A High Level Modeling and Synthesis Methodology for Concurrent Systems Using Rendezvous
Matt Chiu PhD 2011 Accelerating Molecular Dynamics Simulations with High Performance Reconfigurable Systems
Huaxin Dai MS 2010 Energy Minimization Accelerated with FPGAs
Bharat Sukhwani PhD 2010 Accelerating Molecular Docking and Binding Site Mapping using FPGAs and GPUs
Yongfeng Gu PhD 2008FPGA Acceleration of Molecular Dynamics Simulations
Francois Kosie MS 2007 
Josh Model MS 2007FPGA Acceleration of Discrete Molecular Dynamics Simulation
Doug DiSabello MS 2006Fault Tolerant FPGA Co-processing Toolkit (slides)
Tom VanCourt PhD 2006 LAMP: Tools for Creating Application-specific FPGA Coprocessors
Chiaochi Huang MS 2006 Using FPGAs to implement Bayesian Network for reconstructing the Gene Regulatory Networks
Doug DiSabello BS 2004FPGA Acceleration of Microarray Computations
Jinming Ge PhD 2002 Evaluating the Effectiveness of Dynamically-Balanced Adaptive Wormhole Routers
Aparna Mande MS 2002Performance Prediction of Message Passing Communication in Distributed Memory Systems
Mark DeFord MS 2001Test and Integration Environment for PCI Coprocessor Cards
Andreas Svensson MS 2001Computer Simulation of a Web Cache Server with SES/Workbench
Chaitanya Adapa MS 2001Implementation Issues of Building a Multicomputer on a Chip
Calvin Lin MS 2000Simulation Environment for MPI Applications on Multicomputers-on-a-Chip
Honghai Zhang MS 2000 Design of a Computer Vision Coprocessor
Kurt Olin MS 1999Design Tradeoffs of Embedded Networks for Systems on a Chip
Jade Cravy MS 1999A Capacity Planning Environment for NT Servers
Renoy Sam MS 1998Evaluating Performance and Cost of Massively Parallel Array Architectures
Shivshankar Sanikop MS 1998A Fast Flexible Routing Simulator
Anisha Anand MS 1997 Processor/Memory/Array Size Tradeoffs in the Design of SIMD Arrays for Computer Vision Applications
Owais Kidwai MS 1997A Flexible, Efficient Evaluation Environment for Massively Parallel Array Architectures
Anup Pradhan MS 1996An Object Oriented Simulator for Wormhole Routing Networks and Case Studies
 

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Updated  15 Apr 2014