VLSI Graduate Design Project
ENG EC 772
EC772 is a project-oriented course that demonstrates the use of high-level design techniques. There are lectures, milestone presentations, and a final presentation. The lectures, interleaved with tutorials showing the utilization of Verilog, the Cadence RTL compiler, and Silicon Encounter, define the general design flow. Additional design issues are also elaborated in the form of classroom lectures, which take up a fraction of the course class time. Student groups of 2-5 define their own projects, which are scrutinized by the entire class as to difficulty and possibility of success. Milestones entail both oral (presented in class times) and written components. Typically, by the time of the final presentation, the milestone documents can be simply, with test results (not necessarily simple), are combined to demonstrate the veracity of the final chip design. Pay special attention to prerequisites. Verilog is at the heart of almost everything. EC311 and EC413 or equivalent courses can provide the minimal Verilog proficiency for LEAP students. These courses do not qualify for grad student credit, so EC551 (Verilog: may be co-req) or equivalent Verilog skill is necessary. EC571 VLSI Design or strong equivalent proficiency in digital circuits at the transistor level is also essential.
SPRG 2017 Schedule
|A1||Hubbard||TR 3:00 pm-5:15 pm|